Redundant Word Line Switching for Faster Memory Row Replacement
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Solution Overview
Problem
Memory devices require a longer time to select redundant memory cell rows for data storage due to the involvement of redundant control signals and decoding circuits, which slows down the overall operation speed.
Innovation Solution
A memory device with a peripheral circuit containing redundant control switch components that directly transmit redundant control signals to word line drive components, bypassing decoding circuits, allowing direct selection of redundant memory cell rows when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant control signals are transmitted through decoding circuits to select redundant memory cell rows, then the memory device can handle defective rows, but the transmission time increases and overall operation speed decreases
Solution Approach 1:
The patent extracts the redundant control signal transmission path from the conventional decoding circuit path. By providing a direct transmission path for redundant control signals that bypasses the decoding circuits, the invention eliminates the time-consuming decoding step while maintaining the ability to handle defective rows through redundant memory cell rows.
Solution Approach 2:
The patent segments the control signal transmission into two distinct paths: one for normal memory cell row selection through decoding circuits, and another for redundant memory cell row selection that directly transmits control signals. This segmentation allows each path to be optimized for its specific function, with the redundant path being faster.
2Reliability
If decoding circuits are used to process redundant control signals, then comprehensive error handling is achieved, but device complexity increases
Solution Approach 1:
The patent removes the decoding circuit component from the redundant control signal path, extracting only the essential function of transmitting control signals to redundant memory cell rows. This reduces device complexity while maintaining error handling capability through the redundant row mechanism.
3Device complexity
If conventional control signal transmission paths are used for redundant rows, then signal routing is simplified, but transmission speed decreases due to decoding requirements
Solution Approach 1:
The patent segments the control signal transmission into separate physical paths: a conventional path through decoding circuits for normal operations, and a dedicated direct path for redundant row operations. This segmentation resolves the contradiction by allowing each path to be optimized independently - the direct path for speed and the decoding path for comprehensive control.
Solution Approach 2:
The patent introduces separate control signal lines as intermediaries that directly connect the control logic to the redundant memory cell rows without passing through the decoding circuits. These intermediary pathways enable faster transmission while maintaining the ability to route signals appropriately based on whether redundant rows are needed.
Data Source
AI summary
Examples of the present application disclose a memory device, an operation method, a memory system, and a computer system. The memory device includes: a memory array including a first sub-array and a second sub-array, wherein the first sub-array includes a plurality of first memory cell rows, and the second sub-array includes a plurality of second memory cell rows; and a peripheral circuit comprising: a plurality of redundant control switch components coupled to the plurality of second memory cell rows one-to-one; and a word line drive component coupled to each of the plurality of redundant control switch components, wherein each redundant control switch component is configured to: in response to a first redundant selection signal, be in an on state and transmit a corresponding redundant control signal to a corresponding word line drive component; and the corresponding word line drive component is configured to: in response to the redundant control signal, drive a second memory cell row of the plurality of second memory cell rows that is configured to replace the first memory cell row indicated by the input address information.