Semiconductor Memory I/O Layout for HCB Parallel Read-Write
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Solution Overview
Problem
Existing semiconductor memory devices face limitations in fully utilizing advanced packaging methods like Hybrid Copper Bonding (HCB) for high-speed connections, leading to challenges in reducing signal transmission path length and improving bandwidth and latency.
Innovation Solution
A semiconductor memory device utilizing hybrid copper bonding (HCB) for direct electrical connections between chips, enabling simultaneous read and write operations through independent data paths without serialization or deserialization, and optimizing throttling delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional micro bumps are used for electrical connections between chips, then connection reliability is maintained, but signal transmission path length cannot be sufficiently shortened
Solution Approach 1:
The patent introduces an intermediary substrate structure with through-conductors that mediates between the chips, enabling direct electrical connection through the substrate without requiring conventional micro bump connections between chip surfaces. This intermediary approach shortens the signal path while maintaining connection reliability through the structured conductor design.
Solution Approach 2:
The patent transitions from planar surface mounting connections to three-dimensional through-substrate connections. By routing signals vertically through the substrate rather than across chip surfaces, the signal transmission path is dramatically shortened while maintaining reliable electrical contact through the structured conductor array.
2Productivity
If serialization and deserialization components are added to increase bandwidth, then data transfer capacity improves, but device complexity and chip area increase
Solution Approach 1:
The patent segments the data transmission into multiple parallel channels through the through-conductor array, achieving high bandwidth without requiring complex serialization/deserialization logic. Each conductor carries independent data streams simultaneously, providing scalable bandwidth through physical parallelism rather than temporal multiplexing.
Solution Approach 2:
The patent replaces the mechanical/logical complexity of serialization and deserialization circuits with a direct electrical connection system through the substrate. Data is transmitted in parallel through multiple conductors without requiring sequential conversion, eliminating the need for complex control logic and reducing device complexity.
3Speed
If advanced packaging methods like HCB are fully utilized, then connection speed and bandwidth improve, but existing I/O structures cannot fully leverage these advantages
Solution Approach 1:
The patent creates a universal I/O structure where the through-substrate conductor array can accommodate multiple functions including high-speed data transmission, power delivery, and signal routing. This multi-functional design allows advanced packaging methods to be fully utilized across different application scenarios, providing both speed and adaptability.
Solution Approach 2:
The patent implements a dynamic I/O structure where the through-conductor array can be configured and routed to serve different functional requirements. The flexible routing capability allows the same physical structure to adapt to various bandwidth and speed requirements, fully leveraging advanced packaging advantages across different operational modes.
4Adaptability or versatility
If more I/O components and control logic are added to existing memory devices, then functionality improves, but chip area and power consumption increase
Solution Approach 1:
The patent merges the I/O functionality directly into the substrate structure through the through-conductor array, eliminating the need for separate I/O components and control logic on the chip. This integration approach provides enhanced functionality while reducing chip area by moving I/O functions to the packaging level rather than the chip level.
Data Source
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AI summary
A semiconductor memory device (1200), includes, a cell array (1210) including a plurality of memory banks (1210a, 1210b, 1210c, 1210d), a command decoder (1230) configured to decode a read/write command (R&W), a read command (R), and a write command (W) that are input from outside of the semiconductor memory device, an address decoder (1220) receiving a read address (R_ADD) and a write address (W_ADD), an input receiver (1290) configured to transmit write data (W_DATA) input through a write data pad (WDQ) to a global input/output driver (GIODRV) of a memory bank corresponding to the write address (W_ADD), and an output driver (1295) configured to transmit read data (R_DATA) output from an input/output sense amplifier (IOSA) of a memory bank corresponding to the read address (R_ADD) to a read data pad (RDQ), wherein the write data (W_DATA) is input via the write data pad (WDQ) in a single data rate method and transmitted to the global input/output driver (GIODRV) without deserialization processing, and the read data (R_DATA) is transmitted from the input/output sense amplifier (IOSA) to the read data pad (RDQ) without serialization processing. In some embodiments, the semiconductor memory device (1200) is electrically and physically coupled to a central processing unit (1100) by hybrid copper bonding (1006).