DRAM Sense Amplifier Structure Without Edge Reference Arrays
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Solution Overview
Problem
The open bit-line structure in dynamic random access memories (DRAMs) requires additional reference arrays at the edge of each memory cell, increasing chip size and cost.
Innovation Solution
A novel sense amplifier design utilizing a first and second signal amplification unit to amplify voltages within the memory array structure, eliminating the need for edge reference arrays and optimizing the sense amplifier structure to reduce chip size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional reference arrays are provided at the edge of each memory cell in the open bit-line structure, then reference voltage for bit line sense amplification is ensured, but chip area increases
Solution Approach 1:
The patent combines the reference array function with the sense amplifier structure by sharing bit lines between sense amplifiers. The sense amplifier uses bit lines from adjacent memory cells as reference voltages, merging the reference generation function into the existing sense amplifier circuitry rather than requiring separate reference arrays at memory cell edges.
Solution Approach 2:
The sense amplifier is designed to perform multiple functions: it amplifies the signal from the accessed bit line while simultaneously using adjacent bit lines as reference voltage sources. This multi-functional design eliminates the need for dedicated reference arrays, as the sense amplifier structure itself provides both signal amplification and reference voltage generation.
2Reliability
If reference arrays are added to each memory cell edge, then sense amplification reference voltage is available, but device complexity increases
Solution Approach 1:
The patent merges the reference voltage generation function into the sense amplifier circuitry itself. By using adjacent bit lines as references and integrating the reference generation into the sense amplifier's operational structure, the design eliminates separate control logic for reference arrays, reducing overall device complexity.
Solution Approach 2:
The sense amplifier structure serves itself by using adjacent bit lines as reference voltage sources during the sense amplification process. This self-service mechanism eliminates the need for external reference arrays and their associated control logic, as the sense amplifier automatically utilizes available bit line voltages for reference purposes.
Data Source
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AI summary
The embodiments of the present disclosure relate to the technical field of storage, and provide a sense amplifier, a control method therefor, a storage array structure, and a memory. The sense amplifier comprises: a first signal amplification unit, wherein a first end and a second end of the first signal amplification unit are respectively adapted to be electrically connected to a first voltage end and a second voltage end, and a third end and a fourth end of the first signal amplification unit are respectively used as a first node and a second node; and a second signal amplification unit, wherein a first end, a second end and a third end of the second signal amplification unit are respectively adapted to be electrically connected to a third voltage end, a fourth voltage end and a bit line, and a fourth end of the second signal amplification unit is electrically connected to the first node. The sense amplifier is configured to amplify the voltage of the first node to a first voltage or a second voltage in a first signal amplification stage; and to write the second voltage or the first voltage back to a storage unit in a second signal amplification stage. The structure of the sense amplifier in the embodiments of the present disclosure can replace an edge reference array, and no additional reference array needs to be provided, thereby reducing the size of chips and reducing the chip cost.