Pulsed Arbitration for Multi-Port Memory Collision
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Solution Overview
Problem
Existing multi-port memory arbitration systems face issues with data corruption when multiple ports attempt to access the same memory location, particularly due to priority schemes that limit performance by blocking non-priority ports and locking out access for extended clock cycles, especially in scenarios with multiple reads and no writes.
Innovation Solution
A pulsed arbitration system employing a partial-address coincidence detector with a partial-address collision flag and an active global word line detector, which generates a disable pulse related to the writing port's internal write pulse width to deactivate interfering global word lines, allowing simultaneous reads and minimizing blocking duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a priority scheme is used to resolve arbitration conflicts, then data corruption is prevented, but the performance of non-priority ports is significantly limited due to blocking
Solution Approach 1:
The patent implements periodic arbitration pulses instead of continuous blocking. The arbitration mechanism uses timed pulses that periodically check for conflicts and resolve them, allowing ports to access memory during non-conflict periods. This periodic action prevents data corruption during conflicts while maintaining port performance during normal operation.
Solution Approach 2:
The arbitration system dynamically adjusts port access based on real-time conflict detection rather than maintaining static priority assignments. The system activates arbitration only when conflicts are detected, and dynamically grants access rights based on the specific conflict situation, allowing flexible resolution that adapts to different operational scenarios.
2Reliability
If arbitration locks out ports during conflicts, then data corruption is prevented, but ports are blocked for extended clock cycles reducing access speed
Solution Approach 1:
The system uses periodic arbitration pulses with specific timing rather than extended blocking. The arbitration pulse width is carefully controlled to match the minimum required for conflict resolution, allowing ports to resume normal operation immediately after the pulse completes, thus maintaining high access speed while preventing corruption.
Solution Approach 2:
The arbitration mechanism changes the timing parameters of port access dynamically. Instead of fixed blocking periods, the system adjusts the duration and timing of arbitration signals based on the specific conflict situation, optimizing the balance between corruption prevention and maintaining access speed.
3Reliability
If arbitration blocks ports for the winning port's complete clock cycle, then conflicts are resolved, but losing ports experience significant performance reduction due to asynchronous clock cycles
Solution Approach 1:
The patent uses periodic arbitration pulses with controlled width rather than blocking for complete clock cycles. The pulse timing is designed to resolve conflicts without extending to the full duration of asynchronous clock cycles, thereby minimizing the time losing ports are blocked while ensuring reliable conflict resolution.
Solution Approach 2:
The arbitration mechanism applies partial blocking only for the minimum necessary duration to resolve conflicts, rather than blocking for complete clock cycles. This partial action approach uses just enough arbitration signal width to prevent corruption while minimizing impact on losing port performance.
Data Source
AI summary
A pulsed arbitration system has a partial-address coincidence detector with a partial-address collision flag as an output. An active global word line detector and disable pulse generator receives the partial-address collision flag as well as a decoded row address and an internal write pulse as an input, and generates a disable pulse for the interfering global word line of the colliding reading port.