Ferroelectric 3D Memory Cell Structure for Faster Multi-State Erase
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of fine pattern forming technology, making three-dimensional semiconductor memory devices necessary, but these devices face challenges in achieving high integration and efficient data storage.
Innovation Solution
A semiconductor memory device with a substrate, impurity regions, gate insulating layers, and gate electrodes, incorporating ferroelectric materials and charge trap patterns, along with vertical channel structures and conductive pads, to enhance data storage capabilities and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory devices are used to increase integration, then integration density is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with each layer containing impurity regions, gate insulating layers, and gate electrodes. This dimensional change dramatically increases integration density while maintaining manageable device complexity through modular stacking.
Solution Approach 2:
The patent employs nested structures where gate insulating layers are positioned between impurity regions, gate electrodes are formed on the gate insulating layers, and multiple such structures are stacked vertically. The charge trap patterns are embedded within the stack structure, nested between the memory cell layers. This nesting approach maximizes space utilization and increases integration density.
2Loss of time
If conventional memory structures are used, then manufacturing process is simpler, but erase operation time is longer
Solution Approach 1:
The patent introduces charge trap patterns as intermediary structures positioned between the gate electrodes and the channel regions. These charge trap patterns serve as mediators that facilitate faster charge removal during erase operations. The ferroelectric gate insulating layers also act as intermediaries that enable rapid charge switching, significantly reducing erase operation time compared to conventional structures.
Solution Approach 2:
The patent changes the electrical parameters of the memory structure by introducing ferroelectric materials in the gate insulating layers and charge trap patterns. These parameter changes enable faster charge injection and removal rates, directly reducing erase operation time. The different conductivity types of impurity regions also optimize charge transport parameters for faster operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves increased integration and faster erase operations with multiple data states, improving memory performance and reducing operational time.
Implementation Method 1
a ferroelectric pattern interposed between the gate electrode and the charge trap pattern
Implementation Method 2
a charge trap pattern interposed between the ferroelectric pattern and the vertical semiconductor pattern
Data Source
AI summary
A semiconductor memory device may include a substrate, first and second impurity regions on the substrate, first and second gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.