CFET SRAM Bit Line Layout With Frontside-Backside Segmentation
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Solution Overview
Problem
Existing memory circuits face challenges in reducing parasitic resistive and capacitive bit line loading, which affects speed and power performance during read and write operations.
Innovation Solution
The memory macro design includes separate frontside and backside bit line connections for memory cells, utilizing complementary field effect transistor (CFET) devices with stacked pass gates to connect adjacent cells to either a frontside or backside bit line, reducing parasitic loading and maintaining memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional bit line connections are used in memory circuits, then memory cell density can be maintained, but parasitic resistive and capacitive loading increases which degrades speed and power performance
Solution Approach 1:
The bit line connections are segmented into separate frontside and backside bit lines, with adjacent memory cells connecting to different bit lines. This segmentation divides the signal paths to reduce parasitic loading on individual bit lines, thereby improving read and write operation speed while maintaining memory cell density
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking) by implementing frontside and backside bit line connections. Memory cells are arranged in a planar layout but connect to bit lines on opposite sides of the substrate, effectively adding a spatial dimension to reduce parasitic capacitive coupling and resistive loading
2Loss of energy
If separate frontside and backside bit line connections are implemented, then parasitic loading is reduced and speed performance improves, but device complexity increases
Solution Approach 1:
The bit line connections are segmented into separate frontside and backside bit lines, with adjacent memory cells connecting to different bit lines. This segmentation divides the signal paths to reduce parasitic loading on individual bit lines, thereby improving read and write operation speed while maintaining memory cell density
Solution Approach 2:
The CFET pass gate transistors serve multiple functions: they control the connection between memory cells and bit lines, enable selective access to frontside or backside bit lines, and maintain cell isolation. This multi-functionality reduces the need for additional control circuitry, thereby managing device complexity while achieving energy efficiency
Data Source
AI summary
An IC device includes a first complementary field-effect transistor (CFET) static random-access memory (SRAM) cell in a semiconductor wafer, the first CFET SRAM cell including a first internal node and a first pass gate including a first source/drain (S/D) region and a second S/D region electrically connected to the first internal node, and a second CFET SRAM cell in the semiconductor wafer, the second CFET SRAM cell including a second internal node and a second pass gate including a third S/D region and a fourth S/D region electrically connected to the second internal node, wherein the first S/D region is aligned with the third S/D region in a direction perpendicular to a frontside of the semiconductor wafer and a backside of the semiconductor wafer