ECC Memory Addressing Mode Verification Using XOR Logic
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Solution Overview
Problem
Existing memory systems face security issues during changes in addressing modes, leading to potential data breaches, and existing solutions either require significant resource overhead or increase memory size.
Innovation Solution
Implementing a memory system with XOR combinational logic functions to secure data by comparing the addressing mode with error correction codes before and after data storage, using first and second logic circuits to detect errors caused by mode changes, without increasing memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If addressing mode changes are implemented to increase data access flexibility, then adaptability is improved, but data security deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating expected syndrome values for all possible addressing mode transitions during the write operation. The syndrome calculation unit computes what the syndrome should be after mode changes, and this expected value is stored for later comparison during read operations. This advance preparation enables security verification without adding overhead during actual data access.
Solution Approach 2:
The patent implements feedback by comparing the actually read syndrome value with the expected syndrome value that was pre-calculated. The verification unit uses this feedback mechanism to detect whether unauthorized mode changes occurred. If the syndromes don't match, it indicates potential security violations, and the system can respond by rejecting the read operation or triggering security protocols.
2Reliability
If error correction codes are used to detect mode changes, then data security is improved, but device complexity increases
Solution Approach 1:
The patent makes the syndrome calculation unit multi-functional by designing it to calculate syndromes that serve both traditional error detection purposes and security verification purposes. The same circuit that detects bit errors also detects unauthorized addressing mode changes, eliminating the need for separate security verification hardware and reducing overall system complexity.
Solution Approach 2:
The patent changes the parameter being monitored by the error correction system. Instead of only monitoring data integrity parameters, the syndrome calculations now also incorporate addressing mode information. This parameter expansion allows the existing error correction infrastructure to simultaneously provide security verification without requiring completely new hardware.
3Reliability
If security verification during mode transitions is implemented, then data security is improved, but processing time increases
Solution Approach 1:
The patent eliminates verification time during read operations by performing all syndrome calculations in advance during the write operation. The expected syndrome values are pre-computed and stored with the data, so when data is read, verification is simply a matter of comparing the read syndrome with the stored expected syndrome, which takes minimal time.
Solution Approach 2:
The patent performs syndrome calculations for all possible addressing mode transitions during the write operation, even though not all modes will actually be used. This excessive action ensures that the verification during read is extremely simple and fast, as the work has already been done in advance. The trade-off is acceptable because write operations are typically less time-critical than read operations.
Data Source
AI summary
A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.