Column Redundancy Circuits Using Address Prefetch for Higher Speed
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Solution Overview
Problem
Non-volatile memory chips are susceptible to defects during manufacturing or lifespan, leading to reduced production yield and operational speed limitations, necessitating improved redundancy techniques that maintain reliability without compromising speed.
Innovation Solution
Implementing column redundancy systems that prefetch additional bad column addresses during each cycle of the column redundancy system clock, allowing for higher operational speeds by reducing timing path delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional column redundancy systems process bad column addresses sequentially during each clock cycle, then timing path delays increase, but operational speed decreases
Solution Approach 1:
The patent applies preliminary action by pre-fetching multiple bad column addresses into buffer storage during the current clock cycle before they are needed for comparison in subsequent cycles. This anticipatory loading of data eliminates waiting time and reduces timing path delays, allowing the system to operate at higher speeds without compromising the redundancy checking function.
2Reliability
If column redundancy systems implement comprehensive defect checking, then reliability improves, but production yield decreases due to discarding chips with defects
Solution Approach 1:
The patent changes the parameter of defect handling by implementing dynamic column skipping that allows the system to adaptively bypass defective columns while maintaining operational functionality. Instead of discarding entire chips with defects, the system modifies its addressing parameters to skip over bad columns and continue normal operation, thereby maintaining high reliability while preserving production yield.
3Reliability
If column redundancy systems process all bad column addresses in each clock cycle, then completeness of redundancy checking improves, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the bad column address processing into multiple stages: pre-fetching addresses into buffers, comparing addresses in subsequent cycles, and managing multiple buffer storage locations. This segmented approach spreads the processing load across multiple clock cycles and separate functional units, reducing the instantaneous complexity of any single cycle while maintaining complete redundancy checking.
Data Source
AI summary
An apparatus is provided that includes a memory structure including non-volatile memory cells that include a plurality of columns, each column including a column address, and a column redundancy system coupled to the memory structure and a clock signal. The column redundancy system is configured to in a first cycle of the clock signal first compare a first input column address to a first pair of defective column addresses received during an immediately preceding cycle of the clock signal, second compare the first input column address to a second pair of defective column addresses received during the first cycle of the clock signal.