SRAM Write Control via Adaptive Bit Line Discharge
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Solution Overview
Problem
Existing SRAM technologies face challenges in ensuring reliable write operations due to insufficient discharge current or strong pull-up strength, leading to failed data transitions between logic levels during write operations.
Innovation Solution
An SRAM module with a writing control method that adjusts the voltage level of memory cells by discharging them through a bit line, using a simulation memory unit to detect the number of memory cells and generate control signals for adaptive voltage drops, thereby enhancing the reliability of write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the discharge current is increased to ensure complete voltage transition during write operation, then the write reliability is improved, but the power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-discharging the bit line to a lower voltage level before the write operation begins. This preliminary voltage reduction weakens the pull-up current in advance, creating more favorable conditions for the subsequent write operation without requiring excessive discharge current during the actual write process, thus reducing overall power consumption while maintaining reliability.
Solution Approach 2:
The patent changes the voltage parameter of the bit line dynamically. By controlling the bit line voltage to transition from a higher initial level to a lower final level during the write operation, the system adjusts the electrical parameters to optimize both the reliability of data writing and the power consumption. This parameter change allows the write operation to complete successfully with reduced current requirements.
2Reliability
If the pull-up strength of the memory cell is decreased to facilitate voltage transition, then the write operation reliability is improved, but the data retention capability deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-discharging the bit line before the write operation. This preliminary action weakens the pull-up current in advance, allowing the voltage transition during writing to occur more reliably without requiring the memory cell's pull-up transistor to be inherently weaker. The data retention capability is preserved because the memory cell structure remains unchanged, and only the bit line voltage is temporarily adjusted.
Solution Approach 2:
The patent implements periodic action through the sequential timing of operations: first the bit line is pre-discharged to weaken pull-up current, then the write operation occurs, and finally the bit line is recharged to restore normal voltage levels. This periodic sequence allows the system to temporarily modify electrical conditions for reliable writing while maintaining the original memory cell characteristics for data retention when not in write mode.
3Reliability
If the write operation time is extended to ensure complete data transition, then the write reliability is improved, but the productivity decreases
Solution Approach 1:
The patent changes the voltage parameter of the bit line during the write operation, dynamically adjusting it from a higher initial level to a lower final level. This parameter change creates more favorable electrical conditions that accelerate the voltage transition process, allowing the write operation to complete more quickly and reliably without extending the operation time, thus maintaining high productivity.
Solution Approach 2:
The patent applies preliminary action by pre-discharging the bit line before the write operation begins. This preliminary voltage reduction weakens the pull-up current in advance, creating more favorable conditions for rapid voltage transition during the actual write process. As a result, the write operation can complete faster and more reliably without requiring extended time, thereby maintaining high write speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The adaptive voltage adjustment ensures a more reliable write operation by weakening the pull-up current, allowing for smoother data transitions and improved reliability across varying memory cell array sizes.
Implementation Method 1
decreasing the first voltage level corresponding to data retention of the memory cells to a second voltage level by discharging the memory cells
Data Source
AI summary
A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.