DRAM Word Line Nonlinear Discharge for Charge Pumping Reduction
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Solution Overview
Problem
In semiconductor devices like DRAM, the miniaturization of processing sizes leads to increased charge pumping efficiency, causing current increase and potential damage to neighboring memory cells due to minority carriers, and existing methods restrict design freedom and increase area requirements for power supply wiring.
Innovation Solution
A semiconductor device with first and second memory cell arrays, each with a sub-word driver circuit and control units operating at different power supply voltages, nonlinearly deactivates the word line to reduce pumping efficiency and protect surrounding memory cell information, eliminating the need for intermediate power supply wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processing size is miniaturized and trench gate structure is employed, then the off-current of memory cell selecting transistor is reduced, but the gate area and channel length increase, causing charge pump current to increase and potentially damage neighboring memory cells
Solution Approach 1:
The patent applies dynamics by making the word line discharge process non-linear through multi-stage discharge control. The word line is discharged through multiple voltage stages (VDD to 0V, then 0V to VBL) with different discharge rates, rather than a single linear discharge. This dynamic, staged approach reduces the charge pump current peak while maintaining the benefits of miniaturization and trench gate structure.
Solution Approach 2:
The patent changes the discharge parameters of the word line by controlling it to pass through intermediate voltage levels (0V and VBL) during discharge. This parameter-based control transforms the single-stage rapid discharge into a multi-stage controlled discharge, effectively reducing the charge pump current that causes damage to neighboring memory cells while preserving the improved off-current characteristics.
2Object-generated harmful factors
If intermediate potential power supply wiring is added to control word line discharge, then the charge pump current is reduced, but the area of sub-word line driver and cross area increases
Solution Approach 1:
The patent applies universality by making the existing power supply wiring (VDD and VBL lines) serve multiple functions. Instead of adding dedicated intermediate potential power supply wiring, the existing VBL line is reused as an intermediate discharge target for the word line. This multi-functional use of existing wiring reduces charge pump current without requiring additional power supply infrastructure or increasing driver area.
Solution Approach 2:
The patent merges the word line discharge function with the existing bit line voltage reference (VBL). By using VBL as an intermediate discharge level rather than requiring a separate intermediate potential power supply, the patent combines multiple functions into existing structures, avoiding area expansion while achieving charge pump current reduction.
3Area of stationary object
If ground potential is used as intermediate potential, then the wiring area is reduced, but the design freedom for reset waveform is restricted
Solution Approach 1:
The patent changes the intermediate potential parameter from fixed ground potential to variable VBL potential. This allows the reset waveform to be adaptively controlled based on bit line voltage conditions, providing design freedom while using existing wiring infrastructure. The VBL-based intermediate level offers flexibility in waveform shaping without requiring additional wiring area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the pumping efficiency, protects memory cell information, and reduces the area requirements for the semiconductor device while increasing design freedom for the reset waveform.
Implementation Method 1
a charge pumping effect is known, in which minority carriers are injected into a substrate when a MOS transistor is cut off
Data Source
AI summary
Disclosed herein a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate.