Hybrid FeRAM-OxRAM Memory Circuit for Read-Write Energy Balance
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in energy consumption and lifespan due to high numbers of read and write operations, particularly in mobile applications like telephony and autonomous vehicles, necessitating improved energy performance and technological robustness.
Innovation Solution
A hybrid data storage circuit combining FeRAM and OxRAM memory arrays on a single chip, with FeRAM for frequent writing and OxRAM for reading, and a co-integrated data transfer stage to facilitate efficient data transfer between arrays, optimizing operations for neural network phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single non-volatile memory technology is used for both write-intensive and read-intensive operations, then device complexity is reduced, but energy consumption increases and reliability deteriorates due to the inability to optimize for both write and read operations simultaneously
Solution Approach 1:
The memory system is segmented into two distinct memory arrays: a first memory array optimized for write operations and a second memory array optimized for read operations. This segmentation allows each memory type to be tailored for its specific operational requirements, improving overall reliability without significantly increasing system complexity.
Solution Approach 2:
Different memory technologies are assigned to different functional regions: FeRAM is used in the first memory array where high write endurance is required, while OxRAM is used in the second memory array where high read endurance is required. This local optimization of memory quality matches the specific operational demands of each phase.
2Duration of action of moving object
If FeRAM is used for read-intensive operations, then write endurance is improved, but read energy consumption increases due to the destructive nature of FeRAM read operations
Solution Approach 1:
The system segments read operations between two memory types: FeRAM handles write-intensive phases while OxRAM handles read-intensive phases. This segmentation ensures that FeRAM is not subjected to excessive read operations that would consume high energy, while OxRAM's non-destructive reads are used when reading is intensive.
Solution Approach 2:
The system dynamically changes operational parameters by switching between different memory arrays based on the computational phase. During training phases, FeRAM is activated for its write capabilities; during inference phases, OxRAM is activated for its read capabilities, optimizing energy consumption for each operational mode.
3Duration of action of moving object
If OxRAM is used for write-intensive operations, then read endurance is improved, but write energy consumption increases due to OxRAM's higher write energy requirements
Solution Approach 1:
OxRAM is locally deployed in the second memory array specifically for read-intensive operations where its high read endurance and low read energy are advantageous. FeRAM is locally deployed in the first memory array for write-intensive operations where its low write energy and high write endurance are advantageous.
Solution Approach 2:
The system changes operational parameters by switching memory arrays based on the dominant operation type. During training phases requiring frequent writes, FeRAM is used; during inference phases requiring frequent reads, OxRAM is used, thereby optimizing write energy consumption.
4Adaptability or versatility
If data transfer between memory arrays is performed using external converters, then data transfer flexibility is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The data transfer stage is merged with the memory arrays themselves, eliminating the need for external converters. The transfer stage is directly integrated into the memory structure, allowing efficient data transfer between FeRAM and OxRAM arrays while reducing device complexity and manufacturing cost.
Solution Approach 2:
The integrated data transfer stage serves multiple functions: it enables data transfer from FeRAM to OxRAM, supports read operations from both memory arrays, and facilitates write operations to both memory arrays. This multi-functional design provides data transfer flexibility without requiring separate external converter circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances energy efficiency and reliability by leveraging the strengths of both memory technologies, reducing energy consumption and extending lifespan without external converters, while maintaining data integrity and accuracy.
Implementation Method 1
A first memory array of FeRAM (Ferroelectric Random Access Memory) memory units... FeRAM memory units have a high write endurance and a low write energy
Implementation Method 2
A second memory array of OxRAM (Oxide Random Access Memory) memory units... OxRAM memory units have a high read endurance and a low read energy
Data Source
Figure 1a~1b
Figure 2a~2c
Figure 3
AI summary
The present invention relates to a data storage circuit comprising : - a first memory array comprising a plurality of FeRAM memory units; - a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines , a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: o a memory cell having a first electrode and a second electrode connected to the source line associated to said memory unit; oA selection transistor having a gate connected to the word line associated to said memory unit and placed in series with the memory cell between the source line and a bit line associated to of said memory unit; said data storage circuit comprising further: - a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from said common bit line to a transfer voltage applied on a target line of the target OxRAM unit ; said target line corresponding to the word line or the source line and having the same direction as said common bit line.