Multi-Bit Resistive Memory Cell With Low-Voltage Read-Write Split

The memory cell is segmented into distinct functional regions: a first transistor dedicated to write operations and a second transistor dedicated to read operations. This segmentation allows each transistor to be optimized for its specific function, enabling multi-bit storage without requiring higher operating voltages. The write transistor controls voltage application to resistors during programming, while the read transistor enables sensing during readout, decoupling the voltage requirements of write and read operations.

The first node serves multiple functions: it acts as a control terminal for the first transistor during write operations and as a control terminal for the second transistor during read operations. This multi-functionality allows the same node to enable both write and read operations without requiring additional voltage signals, thereby maintaining low operating voltage while achieving multi-bit storage capacity.

Multiple resistors (first resistor, second resistor, third resistor) are merged by coupling their first terminals to the same first node. This merging approach allows multiple data bits to be stored and accessed through a single control node, increasing bit-per-cell capacity while minimizing the number of control lines and reducing overall device complexity compared to using separate control nodes for each resistor.

The device employs dynamic operation modes where the first transistor is activated for write operations to program multiple resistors simultaneously or sequentially through the first node, and the second transistor is activated for read operations to sense data from multiple resistors. This dynamic switching between write and read modes simplifies the control architecture compared to static multi-port designs.

The memory cell is divided into two separate transistor components: a first transistor exclusively for write operations and a second transistor exclusively for read operations. This segmentation improves reliability by preventing interference between write and read operations, as each transistor is optimized for its specific function and operates independently. The first transistor handles high-current write operations while the second transistor handles sensitive read operations, eliminating cross-talk and improving overall cell reliability.

Both the first and second transistors share the same control terminal (first node), which serves as the gate for the first transistor during writes and as the gate for the second transistor during reads. This multi-functionality of the control terminal allows the device to achieve separate write and read transistor functionality without proportionally increasing the number of control nodes, thereby limiting the increase in device complexity.