Memory Glitch Detection with Remote Alarm Confirmation
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Solution Overview
Problem
Existing memory systems are vulnerable to glitch attacks, which can bypass security checks and cause unintended operational failures, and current glitch detection methods do not adequately protect against repeated attacks or ensure reliable alarm triggering.
Innovation Solution
Implementing a combination of hardware-based glitch detection and software-based glitch resistance operations, including randomized delay and redundant signaling through remote glitch detectors, to enhance the resilience of memory systems against glitch attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based glitch detection is implemented, then glitch detection capability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a dedicated glitch detector as an intermediary component that monitors voltage and clock signals separately from the main processing units. This specialized detector acts as a mediator between the physical signals and the processing units, providing glitch detection functionality without requiring the processing units themselves to perform detection tasks, thus adding capability while maintaining architectural clarity.
Solution Approach 2:
The patent implements redundant glitch detectors that create copies of the detection function. Multiple glitch detectors monitor the same signals and provide backup detection capabilities. This copying approach ensures that if one detector fails or is compromised, others can still detect glitches, improving reliability through redundancy rather than through complex single-point detection.
2Reliability
If remote processing units are used for redundant signaling, then reliability against compromised local units is improved, but device complexity increases
Solution Approach 1:
The patent divides the alarm triggering function across multiple independent processing units. Instead of relying on a single local processing unit to trigger alarms, the system segments the alarm triggering capability across multiple processing units. When a glitch is detected, multiple processing units can independently initiate alarm sequences, ensuring that compromise of one unit does not prevent alarm triggering. This segmentation distributes the critical function across the system architecture.
Solution Approach 2:
The patent implements preliminary anti-action by having remote processing units prepared to trigger alarms independently before local units can be compromised. The system anticipates potential local unit compromise and pre-establishes alternative alarm paths through remote units. This preliminary preparation ensures that even if local units are attacked or fail, the alarm function remains available through pre-configured remote alternatives.
3Reliability
If randomized delay operations are implemented, then resistance to repeated glitch attacks is improved, but loss of time increases
Solution Approach 1:
The patent introduces dynamic timing through randomized delay operations. Instead of fixed, predictable timing for security checks and operations, the system dynamically varies timing intervals in a randomized manner. This dynamic approach makes it difficult for attackers to predict when to inject glitches, as the timing targets are constantly changing. The randomness is implemented through software-controlled delay variations that maintain operational functionality while disrupting attack patterns.
4Reliability
If multiple glitch detectors are deployed, then detection coverage is improved, but device complexity increases
Solution Approach 1:
The patent designs glitch detectors with universal functionality that can monitor multiple signal types (voltage and clock signals) using the same basic detection architecture. Each glitch detector is configured to handle different signal monitoring tasks, making the detectors multi-functional. This universality allows the system to achieve comprehensive detection coverage across multiple signals without proportionally increasing the complexity of each individual detector, as they share common detection mechanisms and processing logic.
Data Source
AI summary
A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.