3D Memory Cell Stack With Recessed Word Lines for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge of increasing memory cell density and reducing parasitic capacitance in memory devices is hindered by structural limitations, particularly in three-dimensional semiconductor memory devices.
Innovation Solution
A method involving the formation of a stack body with alternating semiconductor and sacrificial layers, followed by etching to create openings, lateral recesses, and replacing sacrificial dielectric layers with word lines, along with the use of monocrystalline silicon layers and germanium layers to form active layers and capacitors, enhancing the three-dimensional structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase net die, then memory cell density is improved, but parasitic capacitance increases and structural limitations are encountered
Solution Approach 1:
The patent transitions from planar memory cell arrangement to three-dimensional vertical stacking, where multiple memory cells are stacked vertically to form a three-dimensional structure. This dimensional change allows increased memory cell density without proportionally increasing parasitic capacitance, as vertical stacking reduces the lateral area occupied by interconnect structures that generate parasitic capacitance.
Solution Approach 2:
The patent divides the memory device into multiple stacked memory cell layers separated by sacrificial semiconductor layers. Each memory cell is segmented into distinct functional regions (active layers, word lines, bit lines, capacitors) that are independently formed and positioned. This segmentation allows for reduced parasitic capacitance by minimizing the overlap and coupling between adjacent cells while maintaining high density through vertical integration.
2Quantity of substance
If three-dimensional structure is implemented to increase memory cell density, then net die is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs sacrificial semiconductor layers that are formed and processed in advance before the final memory cell structure is completed. These sacrificial layers are used to define the geometry of lateral recesses and to support the formation of word lines and bit lines. By performing these actions preliminarily, the complex three-dimensional structure is built up in a systematic manner, reducing overall manufacturing complexity.
Solution Approach 2:
The sacrificial semiconductor layers serve as intermediary structures during fabrication. They are used to form molds for lateral recesses, to support word line formation, and to define bit line positions. After serving their structural and definitional roles during manufacturing, these sacrificial layers are removed. This intermediary approach simplifies the fabrication process by providing temporary supports and guides that are later eliminated.
3Adaptability or versatility
If lateral recesses are formed to accommodate word lines and capacitors, then memory cell functionality is improved, but etching precision requirements increase
Solution Approach 1:
The sacrificial semiconductor layers serve as precise intermediaries that define the geometry of lateral recesses. By forming the recesses within these sacrificial layers, the etching process benefits from the well-defined boundaries and uniform thickness of the sacrificial material, which simplifies precision control compared to direct etching of the final structure.
Solution Approach 2:
The lateral recesses are segmented into distinct regions for different functions (word line accommodation, capacitor formation, bit line contact). Each segment is formed through controlled etching processes that target specific regions within the sacrificial layer structure. This segmentation allows for precise control of each feature's dimensions and position, reducing the overall precision burden on the etching process.
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a stack body by alternately stacking a plurality of semiconductor layers and a plurality of sacrificial semiconductor layers over a lower structure; forming an opening by etching the stack body; forming a plurality of active layers and a plurality of lateral recesses by etching the semiconductor layers and the sacrificial semiconductor layers through the opening; forming sacrificial dielectric layers partially filling the lateral recesses and contacting the active layers; and replacing the sacrificial dielectric layers with word lines.