Dual-Port Memory Cell Layout Without Strap Cells
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Solution Overview
Problem
As semiconductor integrated circuits become smaller and more complex, the resistance of conductive lines affects the operating voltages and overall performance of digital devices, particularly in memory macros, leading to inefficiencies.
Innovation Solution
A memory circuit design that includes dual-port memory cells with specific configurations of word lines and bit lines on different metal layers, eliminating strap cells to reduce area usage and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional memory cell designs with strap cells are used, then connectivity and signal routing are achieved, but the area occupied by the memory circuit increases
Solution Approach 1:
The patent removes strap cells from the memory circuit design. Strap cells are completely extracted from the architecture, eliminating the need for these additional connectivity elements while maintaining signal routing functionality through alternative means such as optimized word line and bit line configurations.
Solution Approach 2:
The patent utilizes multi-layer metal interconnects (first metal layer, second metal layer, third metal layer) to achieve vertical routing and connectivity. This dimensional transition from planar to three-dimensional routing enables signal transmission without requiring additional in-plane strap cells, thereby reducing the overall circuit area.
2Adaptability or versatility
If more metal layers are added for word lines and bit lines, then signal routing capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnect structure into distinct segments across multiple metal layers: first metal layer for initial routing, second metal layer for intermediate routing, and third metal layer for final connections. This segmentation allows each layer to be optimized independently and simplifies the manufacturing process by breaking down the complex routing into manageable steps.
Solution Approach 2:
The multi-layer metal interconnect structure serves multiple functions simultaneously: it provides signal routing, enables vertical connectivity between different circuit layers, and supports both word line and bit line signals. This multi-functionality reduces the need for separate dedicated structures for each function, thereby simplifying the overall manufacturing process.
Data Source
AI summary
A circuit includes a first dual-port cell, a first and second word line, and a first, second and third bit line. The first word line extends in a first direction, is coupled to the first dual-port cell, and is on a first metal layer above a front-side of a substrate. The second word line extends in the first direction, is coupled to the first dual-port cell, and is on a second metal layer below a back-side of the substrate. The first and second bit line extend in the first direction, are coupled to the first dual-port cell, and are on the first metal layer. The third bit line extends in the first direction, is coupled to the first dual-port cell, and is on at least the second metal layer.