Memory Controller Pad Sequence Reordering for DDR Compatibility
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Solution Overview
Problem
Current memory controllers struggle to simultaneously support both DDR1 and DDR2 memory standards on a single chip, as they require different on-chip designs, external voltages, prefetch sizes, and termination methods, leading to inefficiencies in signal transmission and PCB routing due to mismatched pad sequences.
Innovation Solution
A memory controller with a core logic circuit and a programmable reorderer that selectively connects I/O devices to I/O terminals, allowing for multiple pad sequences to match different trace sequences on printed circuit boards, optimizing support for both DDR1 and DDR2 memory devices by reconfiguring connections based on specific PCB layouts and requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single chip supports both DDR1 and DDR2 memory standards with standardized on-chip designs, then compatibility with both standards is achieved, but pad sequence mismatches cause signal transmission inefficiencies and PCB routing complexities
Solution Approach 1:
The patent implements a programmable reorderer that dynamically reconfigures the connection mapping between I/O terminals and I/O devices based on the detected memory standard (DDR1 or DDR2). This dynamic adaptation allows the same physical chip to optimize its pad sequence configuration for different memory standards, resolving the contradiction between compatibility and signal transmission efficiency.
Solution Approach 2:
The reorderer changes the connection parameter (pad sequence mapping) between I/O terminals and I/O devices depending on the operating mode. When DDR1 is detected, one mapping configuration is applied; when DDR2 is detected, a different mapping configuration is applied. This parameter change enables the system to maintain optimal signal transmission for each standard while supporting both on a single chip.
2Device complexity
If fixed pad sequences are used in memory controllers, then device complexity is reduced, but adaptability to different PCB trace sequences and memory standards is limited
Solution Approach 1:
The patent makes the memory controller universal by adding a programmable reorderer that can adapt to different PCB trace sequences and memory standards. The reorderer acts as a reconfigurable interface layer that maintains the simplicity of the core logic while providing adaptability to various external configurations, allowing the same controller to serve multiple PCB layouts and memory standards.
Solution Approach 2:
The reorderer serves as an intermediary component between the fixed I/O terminals and the variable I/O devices. It mediates the connection by programmatically reordering the signal paths, thereby decoupling the fixed internal structure from the variable external requirements without adding complexity to the core logic circuit.
3Reliability
If separate chips are used for DDR1 and DDR2 support, then optimal performance for each standard is achieved, but device complexity and system integration increase
Solution Approach 1:
The patent merges DDR1 and DDR2 support into a single memory controller chip by incorporating a programmable reorderer that can be configured for either standard. This consolidation maintains the performance optimization of dedicated controllers while reducing system integration complexity, as only one chip needs to be designed, manufactured, and integrated into the system.
Solution Approach 2:
The unified memory controller uses a dynamically reconfigurable reorderer that adapts its connection mapping based on the detected memory standard. This dynamic capability allows a single static chip to provide the performance characteristics of two different dedicated controllers, eliminating the need for separate hardware designs while maintaining optimal performance for each standard.
Data Source
AI summary
Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.