Stacked Complementary NVM Bit Cell for Fast Dense Programming
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Solution Overview
Problem
Existing non-volatile memory (NVM) bit cells face challenges in achieving fast programming while maintaining high memory density due to the bidirectional nature of write signals, which can lead to slower programming and increased power consumption when using a single NMOS transistor, and the use of complementary NMOS and PMOS transistors increases the memory cell footprint.
Innovation Solution
A bit cell design utilizing a stacked complementary transistor pair, where an upper and lower transistor are vertically integrated, allowing bidirectional write signals to be effectively handled, with the upper transistor being an n-type and the lower transistor being a p-type, enhancing switching performance and reducing the lateral footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a single NMOS transistor is used as the access device, then the memory cell footprint is reduced, but programming speed decreases and power consumption increases due to bidirectional write signals
Solution Approach 1:
The access transistor is segmented into two separate transistors (first access transistor and second access transistor) that operate in a complementary manner. Each transistor is optimized for one direction of current flow, with the first transistor handling current flow in one direction and the second transistor handling current flow in the opposite direction. This segmentation allows each transistor to operate in its optimal mode rather than forcing a single transistor to operate in a degraded mode for bidirectional signals.
Solution Approach 2:
Different transistors are used for different directions of current flow based on their specific characteristics. The first access transistor is configured with specific channel width and length parameters optimized for one direction, while the second access transistor has parameters optimized for the opposite direction. This local optimization ensures that each transistor operates at peak performance for its designated direction.
2Productivity
If a complementary NMOS and PMOS transistor pair is used to handle bidirectional write signals, then programming speed improves, but the memory cell footprint increases
Solution Approach 1:
The patent transitions from a planar arrangement of transistors to a vertical stacking architecture. The first and second access transistors are stacked one on top of the other, sharing common source and drain regions. This vertical integration in the third dimension reduces the lateral footprint of the memory cell while maintaining the complementary transistor pair configuration needed for fast bidirectional programming.
Solution Approach 2:
The first and second access transistors share common source and drain terminals, merging their connection points to reduce the overall number of terminals and interconnect structures. This merging of shared components reduces the lateral space required while maintaining the functional independence of each transistor for bidirectional operation.
3Device complexity
If a single NMOS transistor is used, then the circuit complexity is reduced, but power consumption increases due to degenerated mode operation
Solution Approach 1:
The access transistor function is segmented into two specialized transistors, each optimized for one direction of current flow. This segmentation eliminates the need for a single transistor to operate in a degraded, high-power mode when handling bidirectional signals. Each transistor operates in its optimal low-power mode for its designated direction, reducing overall power consumption.
Solution Approach 2:
Each access transistor is configured with specific local parameters (channel width, channel length) optimized for its designated direction of operation. This local optimization ensures that each transistor operates at peak efficiency with minimal power consumption for its specific function, rather than forcing a generic configuration to handle both directions suboptimally.
Data Source
AI summary
A bit cell is disclosed, comprising a non-non-volatile memory element and a transistor arrangement configured to provide a write signal switching a state of the memory element. A first terminal of the memory element is connected to a bit line (BL), a second terminal of the memory element is connected to a first common source/drain terminal of the transistor arrangement, and a second common source/drain terminal of the transistor arrangement is connected to a source line (SL). The transistor arrangement comprises a stacked complementary transistor pair, wherein a gate of an upper transistor is connected to a first word line (WLN) and wherein a gate of a lower transistor is connected to a second word line (WLP). A memory device comprising an array of such bit cells, as well as a method for controlling a bit cell, are also disclosed.