Row Power Gating for Memory Leakage Reduction
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Solution Overview
Problem
Memory devices face challenges in balancing power consumption during retention mode, where they need to reduce leakage current while retaining data in unused rows, as existing technologies either lose data or consume excessive power.
Innovation Solution
The implementation of row driver circuitry with a retention control latch and power gating circuitry that selectively powers or de-powers rows based on a retention signal, allowing for fine-grained retention of data in memory devices, reducing leakage current without losing data in frequently accessed rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory device shuts down into a low power mode by decoupling bitcells from the power rail, then power consumption is reduced, but data values are lost in the bitcells
Solution Approach 1:
The memory array is divided into multiple independently power-gated rows. Each row can be selectively decoupled from the power rail based on whether it contains data that needs to be retained. This segmentation allows the system to power down only the necessary portions of the memory array while keeping other portions active, thus reducing overall power consumption without losing required data.
Solution Approach 2:
The power gating state of each row is dynamically controlled based on the retention control values stored in the latches. When a row is accessed during active mode, the corresponding latch is set to prevent power gating, ensuring the row remains powered and data is retained. This dynamic adaptation allows the system to optimize power consumption in real-time based on actual data retention requirements.
2Reliability
If all rows are kept powered to retain data, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The memory array is divided into multiple independently power-gated rows. Each row can be selectively decoupled from the power rail based on whether it contains data that needs to be retained. This segmentation allows the system to power down only the necessary portions of the memory array while keeping other portions active, thus reducing overall power consumption without losing required data.
Solution Approach 2:
Different rows of the memory array have different power states - some rows are powered to retain data while others are power-gated to save power. This local differentiation of power quality allows the system to maintain data integrity only where necessary while minimizing power consumption in regions where data retention is not required.
3Loss of energy
If row-based power gating is implemented, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The retention control latches are integrated into the existing row driver circuitry, merging the new retention control functionality with the existing memory access logic. This integration approach reduces the overall device complexity by reusing existing circuit structures rather than adding completely separate power gating control circuits.
Solution Approach 2:
The row driver circuitry is designed to serve multiple functions: it controls row selection during active mode and simultaneously controls power gating during retention mode. This multi-functionality reduces the need for separate dedicated power gating control circuits, thereby reducing overall device complexity while still achieving leakage current reduction.
Data Source
AI summary
A memory device and method of operating the memory device are provided. The memory device has bitcells arranged in a plurality of rows and columns. Row driver circuitry provides access to the array of bitcells by selection of an access row of the plurality of rows. The row driver circuitry comprises a retention control latch to store a retention control value and row power gating circuitry responsive to a retention signal to power gate at least one row when the retention control value has a first value and to leave the at least one row powered when the retention control value has a second value. Row-based retention of the content of the bit cells is thus provided, and the leakage current of the memory device when it is in a retention (e.g. sleep) mode, and only some of its rows contain valid data, can thus be reduced.