Dynamic Clock Adjustment for MRAM and SRAM Memory Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computing devices, memory operations such as reading from SRAM cells at low voltages and writing to MRAM cells at low temperatures often exceed a single clock cycle, leading to increased errors and processing delays, which are undesirable for performance.
Innovation Solution
A circuit and method that dynamically adjust the clock signal by incorporating clock-delay components, temperature sensors, and voltage sensors to extend or reduce clock cycles based on operational conditions, ensuring error-free reading from SRAM cells and writing to MRAM cells without significantly reducing processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock frequency is reduced to allow completion of memory operations within a single clock cycle, then the reliability of memory operations is improved, but the processing speed of the computing device deteriorates
Solution Approach 1:
The patent applies dynamics by making the clock signal duration variable rather than fixed. The clock-delay component dynamically extends the clock signal duration based on operational conditions (temperature, voltage, memory operation type), allowing the system to adapt clock timing to match actual memory operation completion times without permanently reducing clock frequency. This resolves the contradiction by providing reliability when needed while maintaining high processing speed during normal operation.
Solution Approach 2:
The patent changes the parameter of clock signal duration based on temperature and voltage conditions. Sensors detect environmental parameters and trigger selective clock extension only when memory operations would otherwise fail to complete. This parameter change approach maintains high processing speed under normal conditions while ensuring reliable memory operation completion when environmental factors cause operation delays.
2Manufacturing precision
If the clock frequency is reduced to ensure error-free memory operations, then the manufacturing precision of memory operations is improved, but the productivity of the computing device deteriorates
Solution Approach 1:
The system dynamically adjusts clock signal duration based on real-time sensing of temperature and voltage conditions. The clock-delay component extends clock cycles selectively only when memory operations are at risk of not completing accurately, rather than continuously reducing clock frequency. This dynamic approach ensures manufacturing precision when needed while maintaining high productivity during normal operating conditions.
Solution Approach 2:
The patent implements feedback through temperature sensors and voltage sensors that continuously monitor operational conditions and provide input to the clock-delay component. This feedback mechanism allows the system to detect when memory operations require extended timing and adjust clock duration accordingly, ensuring accurate memory operations without unnecessarily reducing overall processing throughput.
3Productivity
If selective clock adjustment is implemented to maintain processing speed during normal operation, then the productivity is improved, but the device complexity increases due to additional sensors and control circuitry
Solution Approach 1:
The patent segments the clock control function into separate components: temperature sensors, voltage sensors, a clock-delay component, and the main clock distribution network. This segmentation allows each component to perform its specific function independently, making the complex system more manageable and maintainable while enabling selective clock adjustment to maintain high productivity without requiring complete system redesign.
Solution Approach 2:
The clock-delay component serves as an intermediary between the sensor inputs and the memory operations. It receives temperature and voltage signals, processes this information, and selectively extends clock cycles only when necessary. This intermediary approach manages device complexity by centralizing the control logic in a dedicated component rather than distributing complexity throughout the entire memory subsystem.
Data Source
AI summary
Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.