Vertical Memory Device Double Word Line Structure
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Solution Overview
Problem
The challenge in memory device technology is to increase memory cell density while reducing parasitic capacitance, which is hindered by structural limitations as memory cells are miniaturized.
Innovation Solution
The solution involves creating highly integrated vertical memory cell arrays by vertically stacking memory cells between bit lines and plate lines, with transistors and capacitors arranged laterally and double word lines stacked with an active layer in between to reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase density, then memory cell size is reduced, but parasitic capacitance increases due to structural limitations
Solution Approach 1:
The patent transitions from planar memory cell arrangement to vertical stacking, utilizing the third dimension (height) to increase memory cell density. Multiple memory cells are stacked vertically between bit lines and plate lines, allowing higher integration without increasing footprint area, thereby addressing the contradiction between density and parasitic capacitance
Solution Approach 2:
The memory cell is divided into distinct functional components: transistors positioned between bit lines and word lines, capacitors positioned between plate lines and word lines, with active layers segmented and arranged vertically. This segmentation allows optimized spacing and reduced interference between components, reducing parasitic capacitance while maintaining high density
2Quantity of substance
If memory cells are vertically stacked to increase density, then memory cell density is improved, but structural complexity increases
Solution Approach 1:
The vertical stacking structure serves multiple functions simultaneously: it increases memory cell density, provides natural separation between transistors and capacitors, enables shared bit lines and plate lines across multiple cells, and reduces parasitic capacitance through increased spacing. This multi-functionality reduces overall structural complexity despite the vertical arrangement
Solution Approach 2:
The patent implements a nested structure where active layers are positioned between word lines, capacitors are positioned between plate lines and word lines, and multiple memory cells are nested vertically between bit lines and plate lines. This nested arrangement efficiently packs components while maintaining clear functional separation, managing structural complexity
Data Source
AI summary
A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.