3D Memory Array Layout With CMOS-Above-Array Control
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Solution Overview
Problem
Existing microelectronic device designs face challenges in reducing the size and improving performance due to the presence of control logic devices that impede miniaturization and enhance features like faster memory cell switching, lower threshold voltage, and reduced power consumption.
Innovation Solution
Implementing a CMOS above array (CaA) configuration where control circuitry is vertically positioned above the memory array, utilizing oxide-oxide bonding or a combination of oxide-oxide and metal-metal bonding to separate and attach the control circuitry structure from the memory array structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If control logic devices are provided within a base control logic structure underlying the memory array, then memory operations can be controlled, but the horizontal footprint of the memory device increases
Solution Approach 1:
The patent moves control logic devices from the planar (2D) base control logic structure to the vertical (3D) stacking dimension. Control logic structures are formed above the memory array in the vertical direction, utilizing the Z-axis to reduce the horizontal footprint while maintaining operational control. This dimensional transition allows memory operations to be controlled without increasing the device's planar area.
2Ease of operation
If control logic devices are integrated in the base control logic structure, then memory cells can be accessed, but the size of the memory device cannot be reduced
Solution Approach 1:
The patent implements vertical stacking where control logic structures are positioned above the memory array in the vertical dimension. This allows memory cells to be accessed through vertical interconnects (via structures) that extend from the control logic down to the memory array, enabling full functionality without increasing the device's planar dimensions.
Solution Approach 2:
The patent divides the memory device into separate functional layers: a memory array layer and control logic layers positioned above it. These layers are interconnected through vertical vias and contact structures. This segmentation allows each layer to be optimized independently while reducing overall device footprint through vertical integration.
3Area of stationary object
If control logic devices are positioned above the memory array in a stacked configuration, then horizontal footprint is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the fabrication process into distinct stages: forming the memory array structure first, then separately forming control logic structures, and finally bonding them together through oxide-oxide bonding or metal-metal bonding. This segmentation of the manufacturing process enables each layer to be fabricated using standard CMOS processes before stacking, reducing overall manufacturing complexity despite the advanced packaging requirements.
Solution Approach 2:
The patent employs oxide bonding interfaces and metal bonding interfaces as intermediaries to join the memory array structure with the control logic structures. These bonding interfaces serve as mediators that enable vertical stacking while maintaining electrical and mechanical integrity, facilitating manufacturing through established bonding techniques.
Data Source
AI summary
A microelectronic device comprises a periphery circuitry region, bank regions, a control circuitry structure, and a memory array structure. The periphery circuitry region comprises a central sub-region, and two arm sub-regions extending from the central sub-region from the central sub-region in a first horizontal direction. Each of the two arm sub-regions has a different length than the central sub-region in a second horizontal direction orthogonal to the first horizontal direction. The bank regions are horizontally outward of the periphery circuitry region. The control circuitry structure comprises relatively more speed-critical circuitry within a horizontal area of the periphery circuitry region, and relatively less speed-critical circuitry within horizontal areas of the bank regions. The memory array structure vertically underlies the control circuitry structure and comprises arrays of memory cells within the horizontal areas of the bank regions. Additional microelectronic devices and memory devices are also described.