DRAM Refresh-Integrated Scrubbing for ECC Error Control
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Solution Overview
Problem
The increasing bit errors and decreasing yield in DRAMs due to shrinking fabrication design rules necessitate improved reliability and credibility in semiconductor memory devices.
Innovation Solution
A semiconductor memory device incorporating an error correction code (ECC) circuit, scrubbing control circuit, fault address register, and control logic circuit to perform error detection, correction, and scrubbing operations, with selective codeword correction based on error occurrence counts, and skipping ECC decoding for fault addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase memory capacity, then storage density is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The patent performs preliminary scrubbing operations during idle periods or refresh cycles to proactively detect and correct errors before they affect normal memory operations. The ECC circuit continuously monitors memory cells and performs corrective actions in advance, preventing bit errors from propagating during regular read/write operations.
Solution Approach 2:
The patent implements a feedback mechanism where the ECC circuit continuously monitors error patterns in memory cells and adjusts scrubbing operations accordingly. When errors are detected, the system increases scrubbing frequency for affected regions, creating a closed-loop system that adapts to actual memory health conditions and optimizes reliability maintenance.
2Reliability
If ECC circuit performs error correction on all codewords, then data integrity is improved, but operation time increases
Solution Approach 1:
The patent applies error correction selectively rather than uniformly across all memory operations. The ECC circuit identifies specific codewords or memory regions that require correction based on error patterns, and performs scrubbing operations only on those affected areas. This localized approach maintains data integrity for problematic regions while avoiding unnecessary processing time for error-free data.
Solution Approach 2:
The patent performs partial scrubbing operations during idle periods and refresh cycles, applying error correction to the extent necessary without requiring full scrubbing of entire memory arrays during active operations. This partial action approach maintains adequate reliability while minimizing impact on operational performance.
3Reliability
If scrubbing operations are performed frequently to reduce bit errors, then reliability is improved, but energy consumption increases
Solution Approach 1:
The patent performs scrubbing operations periodically during refresh cycles or idle periods rather than continuously during active memory operations. The ECC circuit schedules scrubbing tasks to coincide with natural memory refresh intervals, ensuring error correction occurs without requiring additional dedicated power cycles or interrupting normal memory access patterns.
Solution Approach 2:
The patent leverages existing memory refresh operations to perform scrubbing tasks, allowing the memory system to service its own error correction needs using already-allocated refresh bandwidth and power resources. The ECC circuit integrates scrubbing operations into the existing refresh infrastructure, avoiding the need for separate dedicated scrubbing power consumption.
Data Source
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AI summary
A semiconductor memory device includes a memory cell array (300), an error correction code (ECC) circuit (400), a fault address register (580), a scrubbing control circuit (500) and a control logic circuit (210). The memory cell array (300) includes memory cell rows. The scrubbing control circuit (500) generates scrubbing addresses based on refresh operations performed on the memory cell array (300). The control logic circuit (210) controls the ECC circuit (400) such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register (580) as a row fault address based on the number of error occurrences.