Burst Order Control Circuit Timing Margin

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Solution Overview

Problem

Conventional semiconductor memory devices face challenges in ensuring accurate and high-speed data output operations due to limitations in burst order control circuits, which affect the timing margin and efficiency of data transmission.

Innovation Solution

A burst order control circuit is designed with a signal transmitting unit, signal delay unit, signal generating unit, and output unit to generate transmission signals based on the output time point of data, ensuring accurate sorting and high-speed operation by using mode signals, delayed read commands, and pipe latch units to manage data from global lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional burst order control circuits are used, then device complexity is reduced, but timing margin for accurate data output deteriorates and high-speed operation is limited

Engineering Contradiction:
Improvetiming margin for accurate data outputVSAvoidcontrol circuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by generating transmission signals in advance based on the output time point of data. The signal generating unit creates transmission signals before the actual data output occurs, allowing the output unit to be prepared ahead of time. This ensures accurate timing margin for data output while maintaining controlled circuit complexity through systematic signal generation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The control circuit is segmented into distinct functional units: signal transmitting unit, signal delay unit, signal generating unit, and output unit. Each unit performs a specific function in the data transmission process. This segmentation allows the circuit to achieve accurate timing control through coordinated operation of simpler modules rather than a single complex unit.

Inventive Principle:
Principle #1Segmentation

2Productivity

If signal generation is synchronized with data output time points, then high-speed operation is enabled, but signal skew and timing errors increase

Engineering Contradiction:
Improvehigh-speed operationVSAvoidsignal timing accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The signal generating unit generates transmission signals in advance based on predetermined output time points. By calculating and preparing signals before the actual data output, the system achieves high-speed operation while maintaining timing accuracy. The preliminary generation allows synchronization without introducing skew, as the signals are ready exactly when needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The signal delay unit incorporates feedback mechanisms to adjust signal timing. By monitoring the actual data output time and comparing it with the generated transmission signal timing, the circuit can compensate for any discrepancies. This feedback loop ensures high-speed operation while preventing signal skew and timing errors.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If data sorting is performed based on start address and interleave mode, then data output order is controlled, but timing margin for high-speed operation deteriorates

Engineering Contradiction:
Improvedata output order controlVSAvoidhigh-speed operation
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The signal generating unit performs data sorting and transmission signal generation in advance based on the start address and interleave mode parameters. By preparing the correct data order and transmission signals before the actual output operation, the circuit maintains ease of operation for data ordering while enabling high-speed operation through pre-positioned signals that eliminate timing delays during the actual data transmission.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8498175B2Burst order control circuit
Publication Date: 2013.07.30 SK HYNIX INC
  • US8498175B2 patent drawing
  • US8498175B2 patent drawing
  • US8498175B2 patent drawing

AI summary

A burst order control circuit includes a signal transmitting unit transmitting a second address as first and second signals in response to a mode signal and a first address, a signal delay unit delaying a read command, the first signal, and the second signal to generate a delayed read command, a first delayed signal, and a second delayed signal, a signal generating unit configured to generate a burst signal in response to the first address and generate first and second transmission signals in response to the delayed read command and the first and second delayed signals, and an output unit sorting and outputting a plurality of data in response to the burst signal, the first transmission signal, and the second transmission signal.