Multi-port Memory Cell Read Disturb Isolation via Segmented Bit Lines
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Solution Overview
Problem
In memory circuits, the interference between write and read operations, known as 'read disturb,' occurs when the voltage level at the write data line affects the data node of a memory cell, causing incorrect voltage levels at the read data line, which can lead to errors in data retrieval.
Innovation Solution
A memory cell design where the write bit line is precharged to a specific voltage level, and the read port transistor is configured to remain off during write operations, preventing interference and maintaining the read bit line at a logical high level until the correct data node voltage is detected, thus minimizing read disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the write data line is precharged to a predetermined voltage level, then the write operation can be performed efficiently, but the voltage level at the write data line interferes with the data node voltage level causing read disturb
Solution Approach 1:
The patent divides the bit line system into separate read bit lines and write bit lines, isolating the read and write operations into independent pathways. This segmentation prevents the precharged write bit line from interfering with the read data node, eliminating read disturb while maintaining write operation efficiency.
Solution Approach 2:
The patent introduces isolation transistors as intermediary elements between the write bit line and the read bit line/data node. These transistors act as controlled switches that prevent the precharged write signal from coupling into the read circuitry, thereby mediating the conflict between write efficiency and read reliability.
2Speed
If the write data line is kept at a predetermined voltage level when not in use, then the write port is ready for quick write operations, but it causes interference with the read data line voltage level
Solution Approach 1:
The patent segments the bit line infrastructure into dedicated read and write bit lines, allowing the write bit line to maintain its precharged state for quick write operations without affecting the read operations. The physical and electrical separation ensures that the harmful voltage interference is confined to the write path only.
Solution Approach 2:
Isolation transistors serve as intermediary components that control the coupling between write and read circuits. When a read operation is active, these transistors remain off, preventing the precharged write bit line from interfering with the read data node, thus eliminating read disturb while preserving write port readiness.
3Ease of operation
If a read word line is activated to access the memory cell, then data can be read from the memory cell, but the interference at the data node affects the voltage level at the read data line
Solution Approach 1:
The patent implements separate read bit lines that are electrically isolated from the write bit lines through isolation transistors. This segmentation ensures that when a read word line is activated, the read data voltage level is not affected by interference from the write circuitry, enabling accurate data retrieval.
Solution Approach 2:
The isolation transistors act as protective intermediaries that block interference from the write bit line from reaching the read data node during read operations. This mediation ensures that the read data line voltage accurately reflects the stored data without being corrupted by write circuit interference.
Data Source
AI summary
A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series between the first data line and the reference node. The first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is between the data node and the second data line. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.