Memory Array Bit Line Layout With Underground Self-Aligned Interconnects
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Solution Overview
Problem
Conventional integrated circuits face challenges in reducing area, power consumption, and noise due to the use of metal wires connecting transistors, which require large diffusion areas and limit the scalability and performance of DRAM structures.
Innovation Solution
The integration of underground interconnection lines embedded into the silicon substrate, allowing for self-aligned connections to transistor source and drain regions, reducing the need for complex surface-level interconnections and enabling multiple signal and voltage distribution levels within the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal wires are used to connect transistors on the surface, then electrical connection is achieved, but the diffusion area increases and lithographic misalignment causes contact holes to be made outside the source or drain regions
Solution Approach 1:
The invention moves the bit line from the surface level to an underground level (below the horizontal silicon surface), creating a vertical dimension change. This allows the bit line to be formed at a different depth where it can self-align with the source/drain regions without being constrained by surface lithographic alignment limitations, thereby resolving the contradiction between manufacturing precision and area requirements
Solution Approach 2:
The invention introduces an intermediary structure (the underground bit line formation process involving etching, deposition, and planarization steps) that mediates between the transistor source/drain regions and the surface-level connection. This intermediary underground layer acts as a buffer zone that eliminates the direct alignment constraints between surface contacts and underlying regions
2Adaptability or versatility
If multiple metal interconnection layers are stacked above the silicon substrate, then signal and power distribution is achieved, but the chip area and complexity increase significantly
Solution Approach 1:
The invention utilizes the vertical dimension by embedding bit lines below the horizontal silicon surface, effectively creating additional interconnection capacity in the depth direction rather than stacking more layers horizontally. This dimensional shift reduces surface complexity while maintaining or enhancing signal distribution capabilities
Solution Approach 2:
The invention segments the interconnection function by separating the bit line function from the surface interconnection layers. The underground bit line handles specific signal paths independently, reducing the complexity and stacking requirements of the surface metal layers while maintaining overall system adaptability
3Reliability
If larger diffusion areas are designed to accommodate photolithographic misalignment, then contact hole placement reliability is improved, but the transistor area and capacitance increase
Solution Approach 1:
By moving the bit line formation to an underground dimension, the invention eliminates the need for enlarged diffusion areas to compensate for surface lithographic misalignment. The vertical offset provides inherent alignment tolerance, maintaining contact reliability without increasing transistor footprint or parasitic capacitance
Data Source
AI summary
A memory array circuit includes a semiconductor substrate, a bit line, a complementary bit line, and a bit line sense amplifier circuit. The semiconductor substrate has an original surface. The bit line sense amplifier circuit is connected to the bit line and the complementary bit line, and the bit line sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first plurality of transistors to the bit line and the complementary bit line; wherein the first set of connection lines is above the original surface of the semiconductor substrate, and the bit line and the complementary bit line are under the original surface of the semiconductor substrate.