Stacked Complementary Bit Cell Layout for Faster NVM Programming
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Solution Overview
Problem
Existing non-volatile memory (NVM) bit cells face challenges in achieving fast programming while maintaining high memory density due to the bidirectional nature of write signals, which can lead to slower programming and increased power consumption when using a single NMOS transistor, and the use of complementary transistors increases the footprint of each memory cell.
Innovation Solution
A bit cell design utilizing a stacked complementary transistor pair, where each transistor has a channel extending along a horizontal track, with a lower transistor at a first level and an upper transistor at a second level, allowing bidirectional write signals to be effectively handled, reducing the lateral footprint, and enhancing memory density through vertical integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single NMOS transistor is used as the access device, then the device complexity is reduced, but the programming speed decreases and power consumption increases due to degenerated mode operation when current flows in the opposite direction
Solution Approach 1:
The patent transitions from a planar single-transistor layout to a vertical stacked configuration. By stacking the NMOS and PMOS transistors vertically with shared source/drain regions, the design utilizes the third dimension (vertical space) to accommodate both transistors within a compact footprint, thereby reducing lateral area while enabling bidirectional current flow for fast programming in both directions
2Productivity
If a complementary NMOS and PMOS transistor pair is used to handle bidirectional write signals, then the programming speed improves, but the footprint of each memory cell increases
Solution Approach 1:
The patent merges the NMOS and PMOS transistors into a compact stacked configuration where they share common source/drain regions. This merging approach allows both transistors to be integrated vertically rather than occupying separate lateral spaces, reducing the overall memory cell footprint while maintaining the bidirectional programming capability provided by the complementary transistor pair
Solution Approach 2:
The design moves from a lateral arrangement to a vertical stacked arrangement, utilizing the vertical dimension to house both transistors. This dimensional transition reduces the lateral footprint of the memory cell while preserving the performance benefits of the complementary transistor pair for bidirectional write operations
Data Source
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AI summary
A bit cell (100) is disclosed, comprising a non-non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal switching a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source/drain terminal (121) of the transistor arrangement, and a second common source/drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor arrangement comprises a stacked complementary transistor pair, wherein a gate (213) of an upper transistor is connected to a first word line (WLN) and wherein a gate (223) of a lower transistor is connected to a second word line (WLP). A memory device comprising an array of such bit cells, as well as a method for controlling a bit cell, are also disclosed.