Fly Bitline SRAM Layout for Dense Simultaneous Read/Write
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Solution Overview
Problem
Conventional dual-port SRAMs face challenges in achieving high density due to the need for extra access transistors, which reduce the number of bitcells that can be implemented in a given area of die space, limiting their efficiency in applications requiring simultaneous read/write operations.
Innovation Solution
A pseudo-triple-port memory bitcell design with a fly bitline configuration is introduced, utilizing a pair of independent wordlines for each bitcell, allowing for simultaneous read and write operations while maintaining density by optimizing metallization layer connections during the BEOL process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual-port SRAM uses extra access transistors for each bitcell to enable simultaneous read/write operations, then read/write performance is improved, but memory density deteriorates due to reduced number of bitcells per die area
Solution Approach 1:
The patent merges the bitline functions by implementing a fly bitline that is shared between two adjacent bitcells. Each bitcell has its own access transistors and wordlines, but the bitline infrastructure is consolidated so that one bitline serves dual purposes for read and write operations across neighboring bitcells, thereby maintaining simultaneous access capability while improving density
Solution Approach 2:
The fly bitline is designed to perform multiple functions: it serves as a bitline for read operations in one bitcell and simultaneously as a bitline for write operations in an adjacent bitcell. This multi-functional design allows the same physical infrastructure to support dual-port operations without requiring separate dedicated bitlines for each function
2Adaptability or versatility
If dual-port SRAM implements two pairs of bitlines per column for simultaneous operations, then operational versatility is improved, but device complexity increases due to additional transistors and interconnects
Solution Approach 1:
The patent combines the bitline pairs by using a fly bitline configuration where a single bitline serves two bitcells simultaneously. This merging approach maintains the ability to perform simultaneous read/write operations (operational versatility) while reducing the total number of bitline interconnects and associated access transistors, thereby simplifying the overall device structure
3Ease of manufacture
If SRAM bitcell layout is optimized for higher density, then manufacturing cost is reduced, but maintaining simultaneous read/write capability becomes more difficult
Solution Approach 1:
The patent segments the bitcell functionality such that each bitcell maintains its own access transistors and wordline control independently, while the bitline infrastructure is shared. This segmentation allows dense packing of bitcells (improving manufacturing efficiency) while preserving the capability for simultaneous read/write operations through the fly bitline mechanism
Data Source
AI summary
A memory includes a bitcell on a substrate, having a bitcell width and a bitcell height and a first access transistor and a second access transistor. The memory includes a first metal layer patterned to form a first pair of wordlines, including a first wordline coupled to a gate of the first access transistor and a second wordline coupled to a gate of the second access transistor. The memory includes a second metal layer patterned to form a pair of second metal layer islands. The pair of second metal layer islands include a first island coupled to the first wordline and a second island coupled to the second wordline. The memory includes a third metal layer patterned to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.