Memory Interface Clock Domain Segmentation for Bandwidth
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Solution Overview
Problem
Conventional SDRAM controllers face challenges in increasing data transfer rates due to the need for higher system bus clock frequencies, which results in excessive overhead, high power consumption, and increased manufacturing costs, making it difficult to design high-speed memory interfaces for medium- and low-priced System-on-Chip (SOC) devices.
Innovation Solution
A memory interface control apparatus and method that applies a memory clock signal with a frequency higher than the system bus clock signal, using a memory controller and clock generator to buffer data and control signals, allowing for increased data transfer bandwidth without increasing the SOC's overhead or manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the system bus clock frequency is increased to increase data transfer rate, then the data transfer rate is improved, but the power consumption and manufacturing cost increase excessively
Solution Approach 1:
The patent divides the clock domain into two separate domains: a system bus clock domain for controlling the SOC and a memory clock domain for controlling the SDRAM. This segmentation allows each domain to operate at its optimal frequency independently, enabling the memory interface to achieve high data transfer rates without requiring the entire system bus to operate at high frequency, thus reducing power consumption and manufacturing costs.
Solution Approach 2:
The patent introduces a clock domain conversion mechanism (including phase interpolators and FIFO buffers) as an intermediary between the system bus clock domain and the memory clock domain. This intermediary enables frequency conversion and data transfer between domains of different frequencies, allowing the memory interface to operate at high speed while the system bus maintains a lower, more power-efficient frequency.
2Productivity
If the system bus clock frequency is increased to increase data transfer rate, then the data transfer rate is improved, but the device complexity and overhead increase
Solution Approach 1:
The patent segments the control architecture into separate clock domains, allowing the memory interface to be controlled independently from the system bus. This reduces system overhead by enabling targeted frequency optimization only where high-speed performance is critical, rather than requiring the entire system to operate at high frequency.
Solution Approach 2:
The patent implements dynamic frequency conversion between clock domains using phase interpolators and programmable delay elements. This dynamic approach allows the memory clock frequency to be adjusted independently from the system bus frequency, enabling flexible optimization of data transfer rates without proportionally increasing system-wide complexity and overhead.
3Productivity
If the memory clock frequency is increased to increase data transfer bandwidth, then the data transfer bandwidth is improved, but the difficulty of design and manufacturing increases
Solution Approach 1:
The patent introduces clock domain conversion circuits (phase interpolators, FIFO buffers, and delay elements) as intermediaries that simplify the manufacturing process. These intermediaries handle the complexity of frequency conversion and timing synchronization, allowing the memory interface to operate at high frequencies without requiring the entire system to be redesigned for high-speed operation, thus reducing design and manufacturing difficulty.
Solution Approach 2:
The patent implements self-synchronizing mechanisms where the memory interface automatically adjusts its timing and phase relationships through feedback from the clock domain conversion circuits. This self-service approach reduces the need for manual timing adjustments and complex external synchronization, simplifying the design and manufacturing process while maintaining high data transfer bandwidth.
Data Source
AI summary
An apparatus and method for controlling a memory interface are provided. The apparatus includes a memory controller controlling a memory and a clock generator applying a system bus clock signal and a memory clock signal to the memory controller. The memory controller applies a memory clock signal having a frequency higher than the frequency of the system bus clock signal to the memory. Accordingly, a high data transfer bandwidth can be obtained with the same cost and effort as for manufacturing a conventional system-on-chip (SOC) while using a memory having a high operating speed.