Write Driver Circuit Low Voltage Bootstrapping
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Solution Overview
Problem
Memories in System-on-a-Chip (SoC) designs face challenges in operating effectively at lower power supply voltage levels, leading to difficulties in storing data due to increased device-to-device variation and reduced margin in circuit design, which affects the performance of memory sub-circuits like sense amplifiers and data storage cells.
Innovation Solution
The implementation of a memory circuit with a boost circuit that initializes a common node to a first voltage level and couples it to a second voltage level lower than the first, using capacitors and MOSFETs to achieve improved write characteristics by bootstrapping the voltage level of a data line below the ground reference, thereby enhancing data storage efficiency at reduced power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If power supply voltage is reduced to accommodate smaller device geometries and thinner insulating layers, then device integration density is improved, but memory sub-circuits such as sense amplifiers and data storage cells fail to operate reliably
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage level of the data line during write operations. The boost circuit temporarily raises the data line voltage above the supply voltage to create a larger voltage swing, which compensates for the reduced effectiveness of transistors operating at lower supply voltages. This allows the memory sub-circuits to maintain reliable operation even when the overall power supply voltage is reduced for higher integration density.
2Ease of manufacture
If power supply voltage is lowered to limit strain on insulating layers, then manufacturing feasibility is improved, but write characteristics of data storage cells deteriorate due to increased device-to-device variation
Solution Approach 1:
The patent implements preliminary action through the boost circuit, which is activated before and during the write operation to pre-charge the data line to a higher voltage level. This preliminary voltage boost ensures that when data is written to the storage cell, the voltage swing is sufficient to overcome device-to-device variations, thereby maintaining fast and reliable write characteristics even at lowered supply voltages.
3Use of energy by moving object
If lower power supply voltage is used in conjunction with manufacturing variation in MOSFETs, then energy consumption is reduced, but memory sub-circuits do not operate as intended
Solution Approach 1:
The boost circuit acts as an intermediary between the low-voltage supply and the data line. It temporarily decouples the data line from the supply voltage by generating a boosted voltage level that is higher than the supply voltage. This intermediary mechanism allows the system to operate at low supply voltage for reduced energy consumption while still providing sufficient voltage swing for reliable memory sub-circuit operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the write characteristics of data storage cells by reducing the time required to store data and allows for reliable operation at lower power supply voltage levels, addressing the limitations of existing memory designs.
Implementation Method 1
The boost circuit may include a plurality of capacitors coupled to the common node. Each of the capacitors may be further coupled to a respective boost node of a plurality of boost nodes.
Implementation Method 2
The first and second write driver circuits may be configured to discharge, dependent on the latched input data, a data line of a selected column into node common between the two write driver circuits.
Data Source
AI summary
Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may be configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.