Semiconductor Output Buffer Control Circuit for Parallel Test Time Reduction
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Solution Overview
Problem
Current semiconductor memory devices, such as DRAMs, face challenges in reducing parallel test time due to limitations in clock cycle duration, which restricts the efficiency of testing multiple chips simultaneously without increasing the number of clocks required.
Innovation Solution
Incorporating a data compression circuit that performs sequential processes based on external clock signal timings, including compressing data in synchronization with one transition, latching it with the next transition, and outputting it with a subsequent transition, thereby shortening the clock cycle from data latching to output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data compression and output processes are performed within the same clock cycle, then the number of clocks required for testing remains low, but the clock cycle duration must be extended to accommodate all operations
Solution Approach 1:
The patent divides the data compression and output process into separate clock cycles. The first clock cycle is dedicated to compressing parallel data from multiple memory cells, while the second clock cycle is dedicated to outputting the compressed data. This segmentation allows each process to be optimized independently and eliminates the need to extend a single clock cycle to accommodate both operations sequentially within the same cycle.
Solution Approach 2:
The patent implements periodic action by using alternating clock cycles for compression and output operations. The compression circuit operates during odd clock cycles while the output buffer operates during even clock cycles, creating a rhythmic, periodic pattern of operations. This approach maintains a consistent, shorter clock cycle duration while still achieving efficient data processing through the alternating sequence of operations.
2Productivity
If multiple chips are tested simultaneously, then testing efficiency increases, but the complexity of data compression and synchronization increases
Solution Approach 1:
The patent merges the data paths from multiple memory cells into a single compression circuit. Instead of providing separate compression circuits for each memory cell or chip, the invention combines all parallel data inputs into one compression unit that processes multiple data streams simultaneously. This merging approach maintains high testing efficiency while reducing the overall number of compression circuits required, thereby simplifying the device architecture.
Solution Approach 2:
The compression circuit is designed with multi-functionality to handle data from multiple memory cells and support various compression ratios. The same compression circuit can process different data widths and adapt to different testing scenarios, eliminating the need for dedicated compression circuits for each specific case. This universal design reduces device complexity while maintaining the ability to test multiple chips simultaneously with high efficiency.
Data Source
AI summary
A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched data.