Gain Cell Memory Shared Drive Lines for Simpler Read-Write Wiring
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Solution Overview
Problem
Gain cell memories have complex wiring structures due to separate reading and writing ports, leading to increased number of lines and drivers, which in turn raises power consumption.
Innovation Solution
A semiconductor storage device with a simplified wiring structure using shared drive lines for both reading and writing operations, utilizing three-dimensional memory cell arrays and transistors to reduce the number of drivers and simplify wiring, enabling non-destructive read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate reading and writing ports are provided with dedicated bit lines and word lines, then reading and writing operations can be performed independently, but the number of lines increases and wiring structure becomes complicated
Solution Approach 1:
The patent merges the reading and writing operations by providing a common bit line that is shared between read and write ports. The memory cell includes transfer transistors that enable data to be transferred to sense nodes for reading operations, while the same bit line structure supports writing operations through controlled transistor switching, thereby reducing the total number of bit lines required
Solution Approach 2:
The bit line is designed with multi-functionality to serve both reading and writing operations. By using transfer transistors and sense nodes that can operate in both read and write modes, the patent eliminates the need for separate dedicated bit lines for each operation, simplifying the overall wiring structure while maintaining operational independence
2Productivity
If separate bit lines and word lines are provided for reading and writing, then data transfer can be performed simultaneously, but the number of drivers increases and power consumption increases
Solution Approach 1:
The patent combines the driver functions by using a single driver circuit to control the common bit line for both reading and writing operations. The transfer transistors and sense nodes are designed to handle both operation types, reducing the total number of driver circuits required while maintaining the capability for simultaneous data transfer through efficient transistor switching control
3Ease of operation
If multiple drivers are provided for separate lines, then reading and writing can be controlled independently, but power consumption increases
Solution Approach 1:
The driver circuit is designed with universal control capability to independently manage both reading and writing operations through the common bit line. The transfer transistors and sense nodes respond to control signals that can selectively enable read or write modes, maintaining independent operational control while using a single driver to reduce power consumption compared to multiple separate drivers
Data Source
AI summary
A semiconductor storage device according to the present embodiment includes a plurality of first data lines and a plurality of first control lines to be used for writing of data, a plurality of second data lines and a plurality of second control lines to be used for reading of data, and a plurality of memory cells. A first drive line is provided in common to the first control lines and the second control lines and transmits a selection voltage for performing writing of data. A plurality of fourth transistors are connected between the first control lines and the first drive line. A plurality of fifth transistors are connected between the second control lines and the first drive line. A plurality of third control lines are connected to gates of the fourth transistors, respectively. A plurality of fourth control lines are connected to gates of the fifth transistors, respectively.