3D Ferroelectric Memory Structure for Higher Switching Efficiency
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Solution Overview
Problem
Current three-dimensional ferroelectric memory devices face challenges in enhancing their electric characteristics, particularly in achieving high integration and efficient switching efficiency while maintaining endurance.
Innovation Solution
The design includes a three-dimensional ferroelectric memory device structure with a channel extending vertically on a substrate, a gate insulation pattern with a larger area than the ferroelectric pattern, and a conductive pattern surrounding the channel, which increases the electric capacitance and enhances the switching efficiency of the ferroelectric pattern, thereby improving the memory window and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional ferroelectric memory device structure is used to achieve high integration, then the integration degree is improved, but the electric characteristics and switching efficiency deteriorate
Solution Approach 1:
The conductive pattern is configured to surround the channel structure, creating a nested arrangement where the gate insulation pattern and ferroelectric pattern are positioned between the channel and the surrounding conductive pattern. This nesting approach increases the electric capacitance without expanding the planar footprint, thereby improving integration density while maintaining electric characteristics.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional structure by stacking the gate insulation pattern, conductive pattern, and ferroelectric pattern in multiple layers around the vertical channel. This dimensional change allows for increased capacitance and improved switching efficiency while achieving high integration degree through vertical space utilization.
2Productivity
If the gate insulation pattern area is increased to improve switching efficiency, then the switching efficiency is improved, but the device area increases
Solution Approach 1:
The gate insulation pattern is extended into the vertical dimension by surrounding the channel in a three-dimensional configuration rather than occupying only planar space. This allows the effective area of the gate insulation pattern to increase for improved switching efficiency while the device footprint remains compact due to vertical stacking.
Solution Approach 2:
The gate insulation pattern is nested within the structure formed by the channel and surrounding conductive pattern, maximizing the use of vertical space. This nested configuration increases the effective gate area for improved switching efficiency without proportionally increasing the overall device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in improved memory window and endurance for the 3D ferroelectric memory device, enhancing its integration degree and switching efficiency.
Implementation Method 1
increases the electric capacitance and enhances the switching efficiency of the ferroelectric pattern
Implementation Method 2
a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern, a gate electrode contacting the ferroelectric pattern
Data Source
AI summary
A three-dimensional ferroelectric memory device includes a channel on a substrate and extending in a vertical direction substantially perpendicular to an upper surface of the substrate, a gate insulation pattern and a conductive pattern stacked on and surrounding a sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate, a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern, a gate electrode contacting the ferroelectric pattern, and first and second source/drain patterns contacting lower and upper surfaces, respectively, of the channel.