Semiconductor Devices TRIZ Cases
- Avalanche Photodetector Layout for Low Dark Current SWIR Detection
A lateral-vertical APD layout separates absorption and multiplication regions to cut dark current and after-pulsing while preserving SWIR sensitivity.
- Multifinger FET Source Via Layout for Inductance Equalization
Position-dependent source vias tune inductance across multifinger FET electrodes, improving gain and high-frequency stability.
- Chip-Level Photodiode Layout for Depletion-Zone Light Absorption
A dopant diffusion layer links top and bottom contacts through the depletion zone, improving photodiode sensitivity and response in chip-level packages.
- Ferroelectric ScAlN Barrier for Switchable p-FET and n-FET Channels
An electric field reverses ScAlN barrier polarization to switch one III-N channel between electron and hole conduction, cutting circuit area.
- Light Detector Gradient Layer for Lattice Mismatch Control
Gradually stepped lattice-constant sublayers relieve epitaxy stress, cut defects and dark current, and improve light detector accuracy.
- 3D Ferroelectric Memory Structure for Higher Switching Efficiency
A vertical channel with surrounding gate insulation and conductive layers boosts capacitance, improving switching efficiency, memory window, and endurance.
- Avalanche Photodetector Layout for Low Dark Current SWIR Sensing
A combined lateral-vertical Ge/Si layout separates absorption and multiplication to cut dark current, after-pulsing, and jitter in SWIR detection.
- Display Panel Conductive Pattern for Low Resistance and Fewer Pseudo Defects
A multilayer conductive pattern with a blocking layer and alloy intermediate layer lowers line resistance while reducing pseudo defects in inspection.
- Metal Field Plate Contact in LDMOS for Drift Region Resistance
By extending a metal field plate contact into shallow trench isolation, this LDMOS case lowers drift resistance while improving transconductance and breakdown voltage.
- Asymmetric P-Type Superlattice for UV LED Hole Injection
An asymmetric p-type superlattice and graded electron blocking layer boost hole injection, conductivity, and UV LED lifetime.
- III-Nitride Dopant Implantation with Group V Stress Relief
Group V co-implantation and graded buffer layers improve dopant activation in III-nitride source and drain regions while limiting lattice stress.
- Organic Charge-Trapping Memory Stack With Composite Retention Layer
An organic-inorganic trapping layer disperses metal oxide in polymer to suppress charge mobility and improve non-volatile memory retention.
- Buried Grid Shield Layout for SiC Voltage Blocking Trade-Off
Intermediate shields between buried grid parts suppress field peaks at Schottky contacts, improving SiC current conduction and voltage blocking.