Multifinger FET Source Via Layout for Inductance Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multifinger-type field effect transistors, the difference in source inductances between source electrodes closest to the ends and those further away leads to unstable high-frequency operation.
Innovation Solution
The semiconductor device incorporates a substrate with source electrodes and via wirings that connect a metal layer, where the inductance between the source electrodes closest to the ends is larger than those further away, stabilizing the operation by adjusting the number and spacing of via wirings to equalize source inductances across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via wirings are added to connect source electrodes to metal layer, then electrical connection is improved, but inductance difference between source electrodes increases causing unstable high-frequency operation
Solution Approach 1:
The patent applies local quality by making the number of via wirings position-dependent. Source electrodes at different positions (first through fourth) are connected to the metal layer through different numbers of via wirings (first number through fourth number respectively), creating localized variations in inductance that compensate for position-dependent inductance differences and achieve overall uniformity.
Solution Approach 2:
The patent changes the parameter of via wiring quantity to control inductance. By adjusting the number of via wirings connecting each source electrode to the metal layer, the inductance of each source electrode is tuned to achieve uniform inductance across all source electrodes, thereby stabilizing high-frequency operation.
2Reliability
If multiple via wirings are used to reduce source inductance, then electrical connection quality improves, but device complexity increases
Solution Approach 1:
The patent segments the via wiring configuration into distinct groups corresponding to different source electrode positions. Each position (first, second, third, fourth source electrodes) has its own designated number of via wirings, creating a systematic segmented structure that manages complexity through organized variation rather than random complexity.
Data Source
AI summary
A semiconductor device includes a substrate, a metal layer provided under the substrate, a plurality of source electrodes provided on the substrate and including first source electrodes and second source electrodes, one or a plurality of first via wirings that overlap with one of the first source electrodes closest to ends of the source electrodes, penetrate through the substrate, and electrically connect the metal layer and the first source electrodes, and one or a plurality of second via wirings that overlap with one of the second source electrodes second closest to the ends of the source electrodes, penetrate through the substrate, and electrically connect the metal layer and the second source electrodes, wherein a first inductance between the one of the first source electrodes and the metal layer is larger than a second inductance between the one of the second source electrodes and the metal layer.