Chip-Level Photodiode Layout for Depletion-Zone Light Absorption

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Solution Overview

Problem

Conventional photodiodes with active structures on the bottom side experience reduced sensitivity and slower response times due to light absorption outside the depletion zone, which is not feasible for chip level packages without compromising performance.

Innovation Solution

A chip level package photodiode design with a dopant diffusion layer connecting the top and bottom conductive layers through the depletion zone, allowing for electrical connection without the need for through silicon vias, enabling smaller form factor and reduced manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If photodiode active structures are placed on the bottom side for chip level package, then device size is reduced, but sensitivity and response time deteriorate due to light absorption outside the depletion zone

Engineering Contradiction:
Improvedevice sizeVSAvoidsensitivity
Core Design Contradiction:
Volume of moving objectVSMeasurement precision

Solution Approach 1:

The patent inverts the conventional photodiode structure by placing the light-absorbing active structures on the bottom side of the chip, opposite to the conventional top-side placement. This inversion enables chip level packaging while maintaining performance through the dopant diffusion layer that ensures proper electrical connection through the depletion zone

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The dopant diffusion layer acts as an intermediary element that facilitates electrical connection between the top and bottom conductive layers through the depletion zone. This mediator enables the bottom-side active structures to function properly in chip level packages without compromising sensitivity or response time

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If conventional photodiode structure with top-side anode and bottom-side cathode is used, then electrical connection is straightforward, but device height and complexity increase for chip level package applications

Engineering Contradiction:
Improveelectrical connectionVSAvoidpackage structure
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the electrical connection functions by using a single dopant diffusion layer that simultaneously connects both the anode and cathode through the depletion zone, eliminating the need for separate through-silicon via structures and reducing overall package complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the electrical parameters by modifying the doping concentration and diffusion depth of the dopant diffusion layer to optimize electrical connection through the depletion zone, enabling proper functionality with reduced structural complexity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances sensitivity and response time by ensuring light absorption within the depletion zone, while allowing for direct soldering to a printed circuit board, suitable for space-constrained applications like wearable devices.

Implementation Method 1

A dopant diffusion layer is formed between the first conductive layer and the first contact electrically connecting the first conductive layer to the first contact, the dopant diffusion layer proceeding from the first side of the chip level package photodiode to the second side of the chip level package photodiode completely through a depletion zone of the chip level package photodiode

Methodology Applied
Scientific EffectDopant diffusion: Diffusion

Data Source

PatentUS20240162355A1Chip level package photodiode
Publication Date: 2024.05.16 VISHAY SEMICON GMBH
  • US20240162355A1 patent drawing
  • US20240162355A1 patent drawing
  • US20240162355A1 patent drawing

AI summary

A chip level package photodiode includes a first conductive layer located at a first side of the chip level package photodiode. A first contact is located at a second side of the chip level package photodiode. A dopant diffusion layer is formed between the first conductive layer and the first contact electrically connecting the first conductive layer to the first contact, the dopant diffusion layer proceeding from the first side of the chip level package photodiode to the second side of the chip level package photodiode completely through a depletion zone of the chip level package photodiode.