3D Ferroelectric Memory Tiers for High Density and Low Leakage
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Solution Overview
Problem
Existing 3D memory devices, such as 3D NOR-type memory, face challenges in achieving optimal memory cell density and reducing leakage current between vertically stacked memory cells, which affect device performance.
Innovation Solution
A 3D memory device design with stacked tiers of memory cells separated by a dielectric material and gate structures that include a ferroelectric layer and conductive pillars, allowing for increased cell density and reduced leakage current through the use of a gate-all-around configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stacked memory cells are implemented to increase integration density, then memory cell density is improved, but leakage current between vertically stacked memory cells increases
Solution Approach 1:
The memory device is divided into multiple tiers separated by isolation dielectric layers. Each tier contains memory cells that are electrically isolated from adjacent tiers, preventing leakage current while maintaining high vertical integration density. The isolation dielectric material creates distinct segments between stacked memory cell layers.
Solution Approach 2:
An isolation dielectric layer is introduced as an intermediary material between vertically stacked memory cells. This dielectric layer acts as a barrier that blocks leakage current paths while allowing the memory cells to maintain their stacked configuration for high density.
2Productivity
If geometry size is scaled down to increase functional density, then productivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to 3D stacked architecture. By utilizing the vertical dimension, the device achieves higher functional density without further reducing lateral geometry size, thereby avoiding the associated manufacturing complexity while maintaining improved productivity.
Solution Approach 2:
Multiple memory cell tiers are nested vertically within a compact footprint. Each tier contains complete memory cells with source/drain regions, channel regions, and gate electrodes that are stacked one above another, maximizing space utilization and production efficiency without requiring proportionally smaller feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances memory cell density and improves device performance by facilitating miniaturization and simplifying routing layouts while effectively utilizing chip area, thus increasing integration density.
Implementation Method 1
Each of the gate structures may include a conductive pillar and a ferroelectric layer wrapping the conductive pillar
Implementation Method 2
The memory device includes first and second isolation dielectric layers disposed between the first and second tiers
Data Source
AI summary
Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.