3D Ferroelectric NOR Memory Using Partial Polarization Reference States
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Solution Overview
Problem
Current three-dimensional NOR memory arrays face challenges in optimizing read, program, and erase operations for enhanced performance, particularly in achieving multi-bit storage and reducing electrical stress on ferroelectric memory transistors.
Innovation Solution
Implementing a partial polarization scheme in three-dimensional arrays of NOR memory strings with thin-film ferroelectric memory transistors, which allows for additional polarization states by modifying bias voltages and durations, enabling the use of ferroelectric memory transistors as both data storage and reference transistors without additional processing or materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If full polarization states are used in ferroelectric memory transistors, then storage capacity is improved, but electrical stress and power consumption increase
Solution Approach 1:
The patent applies partial polarization states (e.g., +0.5Pc, -0.5Pc) instead of full polarization states (+Pc, -Pc) in ferroelectric memory transistors. This partial action approach maintains sufficient storage capacity differentiation while reducing the electrical stress and power consumption associated with achieving full polarization saturation.
2Quantity of substance
If full polarization states are used in ferroelectric memory transistors, then storage capacity is improved, but endurance cycling deteriorates
Solution Approach 1:
By using partial polarization states rather than full polarization, the patent reduces the electrical stress applied to the ferroelectric material during write operations. This partial action preserves the necessary storage capacity differentiation while minimizing degradation of the ferroelectric material, thereby improving endurance cycling and device reliability.
3Measurement precision
If reference signals are generated using separate reference memory transistors, then read operation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent makes the ferroelectric memory transistor structure universal by enabling it to serve both as a data storage cell and as a reference signal generator. By programming reference memory transistors with known partial polarization states, the same transistor architecture performs multiple functions, eliminating the need for separate reference signal generation circuits and reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves erase and write endurance, enables multi-bit storage in each ferroelectric memory transistor, and provides a stable reference signal for read operations, enhancing the overall performance and reliability of the memory device.
Implementation Method 1
each ferroelectric memory transistor including a ferroelectric gate dielectric layer that is polarizable in response to application of bias voltages to the drain, source and gate terminals
Data Source
AI summary
A memory structure including three-dimensional NOR memory strings and method of operation is disclosed. In some embodiments, the memory device implements partial polarization to provide a reference signal for read operation. The reference signal realizes a third logical state distinguishable from the first and second logical stages in the ferroelectric memory transistor, such as associated with the program and erase states. In another embodiment, the memory device provides a reference signal for read operation by averaging a first signal associated with a program state and a second signal associated with an erased state of the ferroelectric memory transistor. In some embodiments, the memory device implements one or more partial polarization states to provide a multi-level memory cell with more than one logical bit stored in each memory cell.