A FinFET MTP cell with dual storage nodes and metal gates overcomes thin-oxide and metal-gate scaling bottlenecks in embedded non-volatile memory.
A stepped discharge portion penetrating the source line drains positive charge during high-aspect-ratio etching to suppress arcing and improve yield.
Tailored reticles and elliptical contacts compensate for pillar bending in stacked memory, improving overlap, conductivity, and reliability.
Undoped channel regions beside select lines stabilize GIDL current during erase and improve reliability in highly stacked 3D memory.
A FinFET MTP cell uses a silicon nitride storage gate and metal control gate to improve programming, erasing, and read-state separation.
Alternating sacrificial layers and confined epitaxial growth form dense stacked lateral semiconductor structures with fewer lithography and annealing steps.