FinFET MTP Memory Cell With Dual Storage Nodes for eNVM Scaling
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Solution Overview
Problem
Conventional multi-time programmable (MTP) non-volatile memory cells face challenges due to bottlenecks in thin oxide and metal gate processes during technology shrinking, affecting the efficiency and density of embedded non-volatile memory (eNVM).
Innovation Solution
The development of a novel MTP memory cell utilizing a Fin field effect transistor (FinFET) structure with two storage nodes and corresponding metal control gates, allowing for independent programming and reading of bits, and fabricated using a cut metal gate sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating polycrystalline gate structure is used, then charge storage function is achieved, but process bottleneck occurs during technology shrinking
Solution Approach 1:
The patent changes the material parameters of the gate structure from conventional floating polycrystalline silicon to metal gate electrode layers (such as tungsten, titanium nitride, or tantalum nitride), and modifies the dielectric layer composition to high-k materials. This parameter change maintains the charge storage function while enabling compatibility with advanced technology nodes and resolving the process bottleneck during technology shrinking.
Solution Approach 2:
The patent employs a composite structure consisting of metal gate electrode layers combined with high-k dielectric materials (such as hafnium oxide, zirconium oxide, or aluminum oxide). This composite material approach achieves both the required charge storage capability and process compatibility, eliminating the bottleneck faced by conventional single-material gate structures during technology scaling.
2Quantity of substance
If memory cell density is increased, then storage capacity improves, but programming and erasing efficiency decreases
Solution Approach 1:
The patent divides the gate structure into separate control gate and storage gate components, with each serving distinct functions. The control gate handles programming and erasing operations while the storage gate maintains charge. This segmentation allows high-density cell arrangement without compromising programming and erasing efficiency, as each gate can be optimized independently for its specific function.
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional FinFET channel structures with gates wrapping around the channel. This dimensional change enables higher cell density through vertical stacking while maintaining efficient electric field control for programming and erasing operations, thus improving both density and efficiency simultaneously.
3Length of moving object
If thin oxide process is used, then device scaling is achieved, but manufacturing bottleneck occurs
Solution Approach 1:
The patent replaces thin oxide dielectric layers with high-k dielectric materials that provide equivalent or superior electrical performance at greater physical thickness. This parameter change allows device scaling to continue while avoiding the manufacturing bottlenecks associated with ultra-thin oxide processes, as the high-k materials can be deposited using standard atomic layer deposition (ALD) techniques at thicker, more manufacturable dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-density memory cell arrangements with improved efficiency in programming and erasing operations, maintaining data integrity even when power is removed, thus addressing the limitations of conventional eNVM technologies.
Implementation Method 1
a control gate electrode layer disposed on the storage gate electrode layer
Implementation Method 2
The MTP memory cell includes a Fin field effect transistor (FinFET) having two or more storage nodes
Data Source
AI summary
Embodiments the present disclosure provide a MTP memory cell comprising two or more bits. The memory cell includes a FinFET transistor having two or more storage nodes formed around a channel region, and two or more gate electrodes formed over the two or more storage nodes. The memory cell may be implemented by either n-channel transistor or p-channel transistor.