3D Memory Channel Structure for Stable GIDL During Erase
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Solution Overview
Problem
The operational reliability of three-dimensional (3D) semiconductor memory devices is compromised as the number of stacks of memory cells increases, leading to deteriorated performance.
Innovation Solution
The semiconductor memory device incorporates a stacked body with interlayer insulating layers and select lines, a core insulating layer, semiconductor patterns with undoped areas, doped semiconductor patterns, and a gate insulating layer to enhance operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacks of memory cells is increased to improve the degree of integration, then the area occupied by memory cells per unit area is reduced, but the operational reliability of the 3D semiconductor memory device is deteriorated
Solution Approach 1:
The patent applies local quality by creating undoped areas within the semiconductor pattern at specific locations between the select line and core insulating layer. These localized undoped regions modify the electrical properties only in critical areas where GIDL current occurs, rather than changing the entire semiconductor structure. This allows the device to maintain high integration with multiple stacks while improving operational reliability by stabilizing GIDL current in specific problem areas.
Solution Approach 2:
The patent changes the doping parameter of the semiconductor pattern by introducing undoped areas alongside doped regions. This parameter modification affects the electrical characteristics of the channel, specifically reducing and stabilizing GIDL current during erase operations. By adjusting the doping state in specific regions, the patent resolves the contradiction between maintaining high integration and ensuring operational reliability.
2Area of stationary object
If the number of stacks of memory cells is increased, then the area efficiency is improved, but the channel current characteristics and GIDL current stability are deteriorated
Solution Approach 1:
The patent introduces undoped areas within the semiconductor pattern at specific locations between the select line and core insulating layer. These localized undoped regions modify the electrical properties only in critical areas where GIDL current occurs, rather than changing the entire semiconductor structure. This allows the device to maintain high integration with multiple stacks while improving operational reliability by stabilizing GIDL current in specific problem areas.
Solution Approach 2:
The patent changes the doping parameter of the semiconductor pattern by introducing undoped areas alongside doped regions. This parameter modification affects the electrical characteristics of the channel, specifically reducing and stabilizing GIDL current during erase operations. By adjusting the doping state in specific regions, the patent resolves the contradiction between maintaining high integration and ensuring operational reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the channel current characteristics and stabilizes the gate-induced drain leakage (GIDL) current during erase operations, thereby enhancing the operational reliability of the semiconductor memory device.
Implementation Method 1
forming a gate insulating layer by oxidizing a part of the doped semiconductor layer through the gate region
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers, a core insulating layer penetrating the stacked body, a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and the core insulating layer, doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers, and a gate insulating layer disposed between the semiconductor pattern and the select line.