3D FET Switch Array Stacking With Hybrid Bonded IC Dies
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Solution Overview
Problem
Existing 2-D integrated circuit (IC) dies face challenges in reducing their planar footprint while maintaining high performance, especially in radio frequency (RF) circuitry, due to parasitic resistances, capacitances, and inductances.
Innovation Solution
The development of 3-D integrated circuit structures and circuits using hybrid bonding interconnects (HBI) technology, which stacks and bonds aligned IC dies to reduce the planar area while maintaining high performance FET switch arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 2-D planar IC die structure is used, then manufacturing and routing are simpler, but the planar footprint area increases
Solution Approach 1:
The patent transitions from a 2-D planar IC die structure to a 3-D stacked structure by bonding multiple IC dies vertically. This dimensional change allows circuit functionality to be distributed across multiple layers, significantly reducing the planar footprint area while maintaining or enhancing performance through optimized signal routing in the vertical dimension.
2Productivity
If more transistors are added to increase functionality, then electronic performance improves, but the planar footprint area increases
Solution Approach 1:
The patent distributes increased transistor count and circuit functionality across multiple vertically stacked IC dies rather than expanding horizontally. This allows higher productivity in terms of electronic functionality while reducing planar footprint area by utilizing the vertical dimension for additional circuit layers.
Solution Approach 2:
The patent divides the overall circuit functionality into separate IC dies that are stacked vertically. Each die contains specific circuit blocks or functional units, allowing independent optimization and integration. This segmentation enables increased total transistor count and functionality without proportionally increasing the planar footprint area.
3Area of stationary object
If 3-D stacked structure is used, then planar footprint area is reduced, but parasitic resistances and inductances increase
Solution Approach 1:
The patent implements different interconnect approaches for different signal types and functional blocks within the 3-D stacked structure. By optimizing local interconnect characteristics (conductive material selection, via dimensions, bonding interface quality) for specific signal requirements, the patent reduces parasitic resistances and inductances in critical paths while maintaining the reduced planar footprint area benefits of 3-D stacking.
Data Source
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AI summary
Three-dimensional (3-D) integrated circuit structures and circuits that enable high performance FET switch arrays while consuming less planar area than conventional 2-D IC dies. In one embodiment, an integrated FET switch circuit includes a first wafer/die including a first set of groups of FET cells, and a second wafer/die joined to the first wafer/die through hybrid bonding interconnects and including a second set of groups of FET cells, wherein a first side drain bus of each group in the first wafer/die is connected through the hybrid bonding interconnects to a second side source bus of a first corresponding group in the second wafer/die; and wherein a second side source bus of each group in the first wafer/die is connected through the hybrid bonding interconnects to a first side drain bus of a second corresponding group in the second wafer/die.