3D High-Voltage Fin Transistors With Dielectric Liners for Isolation
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Solution Overview
Problem
Conventional fabrication approaches struggle to support high voltage transistors on aggressively scaled three-dimensional device architectures due to reduced isolation thickness between gate and source/drain contacts, leading to premature device failure and reliability issues.
Innovation Solution
The implementation of an inside spacer dielectric liner process, which includes the deposition of multiple conformal dielectric layers to increase the spacing between the gate and source/drain contacts, using a replacement metal gate process flow to provide additional dielectric margin and improve high-voltage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication approaches are used for scaled three-dimensional devices, then manufacturing simplicity is maintained, but isolation thickness between gate and source/drain contacts is reduced leading to premature device failure
Solution Approach 1:
The fabrication process is divided into distinct stages: forming mandrels, depositing first spacers, removing mandrels, depositing dielectric liner, and forming second spacers. This segmentation allows each step to be optimized independently, with the dielectric liner specifically addressing the isolation thickness issue without requiring complete process redesign
Solution Approach 2:
The dielectric liner is deposited in advance before final contact formation, pre-establishing the required isolation thickness between gate and source/drain contacts. This preliminary action ensures that when contacts are later formed, the minimum isolation requirements are already satisfied, preventing premature device failure
2Quantity of substance
If device dimensions are reduced to increase density, then capacity is increased, but isolation thickness is reduced causing reliability issues
Solution Approach 1:
The dielectric liner provides locally enhanced isolation properties at critical interfaces (gate-to-contact regions) without requiring uniform increase in isolation thickness throughout the entire device structure. This allows high-density scaling while maintaining reliability at specific stress points through targeted dielectric reinforcement
3Area of moving object
If spacing between gate and source/drain contacts is reduced for scaling, then device density increases, but device breakdown occurs
Solution Approach 1:
The dielectric liner acts as an intermediary layer between the gate and source/drain contacts, providing additional electrical isolation that enables reduced spacing without compromising breakdown voltage. This intermediary dielectric layer allows the structure to withstand higher electric fields that would otherwise cause breakdown in directly contacted configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability of high-voltage transistors by increasing the gate-to-contact spacing, supporting higher voltage supplies and maintaining transistor performance, even at scaled densities, thereby addressing the limitations of conventional approaches.
Implementation Method 1
deposition of multiple conformal dielectric layers to increase the spacing between the gate and source/drain contacts
Data Source
AI summary
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.