Solid-State Devices TRIZ Cases

A p-type III-N depleting layer smooths electric fields while preserving small gate-drain spacing, enabling low on-resistance and high breakdown voltage.

Varying ohmic and silicide contact density across a JBS chip spreads surge current, limits hot spots, and preserves low forward voltage.

A curved micro LED top surface reduces internal reflection to improve light extraction and widen beam angle without added optics.

A gated transistor ESD path replaces diode-heavy protection to cut pad capacitance, save area, and support dense packaging.

Selective light-blocking over non-emission electrode areas cuts external reflection while preserving pixel light efficiency and visibility.

Copper LED connections are heated to widen gaps for ALD protective film coverage, improving corrosion resistance and short-circuit reliability.

Multiple sub-meta lenses in silicon shorten optical paths, reduce angular response, and improve pixel sensor SNR in thinner image sensors.

A widened source subregion adds resistance to parasitic STI-edge paths, cutting subthreshold hump, leakage current, and analog noise.

A segmented resin with reflective and absorbing regions improves light extraction and contrast after element substrate removal.

A package barrier blocks molding compound from optical and temperature-sensitive components, preserving exposure, reliability, and lower package height.

Selective cover-unit sealing vacuum-packages only normal electronic units, improving vacuum quality while reducing packaging waste.

Grooved side printing with matched protrusions and hydrophobic walls confines conductive liquid to cut open and short circuits in mini and micro LED panels.

Segmented transparent common electrode lines align liquid crystal molecules while increasing transmittance and reducing dark fringes.

Quantum dots placed in porous semiconductor layers with passivation reduce surface-defect losses and enable wavelength conversion in miniaturized LEDs.

Porous semiconductor layers with quantum dots and passivation reduce surface defects and improve micro-LED luminous efficiency for displays.

A dual-scintillator detector layout boosts x-ray conversion while limiting optical blurring and manufacturing cost through filtered light transmission.

A partial light-shielding overlap across module gaps cuts light interference while preserving dense layout and stable electrical connections.

A nested P/N-doped protection structure diverts plasma charge from pixel transistors while preserving breakdown voltage and image sensing operation.

Air gaps in DRAM cylindrical capacitor top electrodes block boron diffusion into the dielectric, cutting leakage and improving reliability.

Grouped bit lines and selective line activation let stacked 3D memory cells read in parallel with lower power use and less gate disturbance.

A dual-emission sub-pixel with color conversion offsets red LED efficiency loss at high PPI while improving gamut and lowering current density.

A thicker disc shutter protects the stage during pre-sputtering while stage-mask spacing is adjusted to avoid interference and startup delay.

A radially varying microlens curvature preserves phase-difference focus detection while suppressing crosstalk between adjacent pixels.

A trench-shaped conductive film lowers wiring resistance while keeping copper coverage low enough to prevent bonding voids in stacked image sensors.

A recessed substrate filled with dielectric brings optical fibers closer to waveguides, cutting loss and improving photonic package communication.

Bias switching between reverse and forward states lets a dynamic photodiode detect single photons at lower voltage with tunable sensitivity.

An integrated lens pattern beneath the light emitting element boosts optical efficiency and viewing angle while avoiding extra process complexity.

Gapped partition walls create bendable pixel chambers that raise aperture ratio, speed refresh, and reduce image sticking in electrophoretic displays.

Separating the light emitting element area from the sub-pixel area simplifies display fabrication, cuts process cost, and improves light efficiency.

By distributing passive and active VR components across stacked dice, this case boosts current capability and efficiency in a smaller package.

Different transparent-area and pixel geometries create region-specific transmittance in a display panel, supporting under-screen optical sensors.

Transparent capacitor electrodes and oxide TFTs raise aperture ratio, speed particle response, cut energy use, and prevent image sticking.

A through-hole organic layer stack improves pixel aperture ratio, contrast, and transmittance while supporting higher display process yield.

A high-aperture electrode and line layout strengthens charged particle motion to improve refresh speed, contrast, and color in electrophoresis displays.

A single-active-area ESD structure places emitter and collector in one active region to cut die area and improve low-voltage operation.

An insulating layer on the wafer edge and slope weakens dicing tape adhesion, reducing peeling damage and improving semiconductor yield.

Embedded microLEDs, waveguides, and substrate photodetectors enable dense optical chip links with lower latency and power than electrical interconnects.

A movable lens replaces powered module motion to simplify optical coupling alignment, cutting setup complexity, time, and handling cost.

A backside power rail and contact jumper tie gate turn-off voltage through S/D contacts, enabling electrical diffusion break in smaller standard cells.

Series-connected MOS transistors and RC trigger circuits limit normal-state voltage stress while enabling controlled ESD current discharge.

Single diffusion breaks segment ESD guard ring fins to cut protection volume, prevent long-strip collapse, and preserve semiconductor performance.

Monolithic RGB InGaN platelets grown on one epiwafer avoid mass transfer, improve red emission, and preserve efficiency in sub-10 µm microLED pixels.

An omega-shaped semiconductor stack and segmented electrodes reduce short-circuit defects while preserving electrical connection reliability.

Isolation trenches replace buried oxide in monolithic semiconductor assemblies, cutting SOI cost while improving heat dissipation.

Lower carrier concentration in the sensing IGBT delays sensing current rise, suppressing switching voltage spikes and false overcurrent trips.

A split lower-upper stack and separation pattern isolate adjacent drain select plugs to speed memory access while preserving data integrity.

Liquid metal pixel and bus wires help stretchable micro-LED displays resist cracking under deformation while maintaining stable electrical operation.

An axially symmetric void in the prism layer equalizes light reflection paths, reducing astigmatism, aberration, and sub-pixel crosstalk.

A shared bonding layer replaces multiple bottom pads in a micro LED panel, simplifying backplane connection while lowering process complexity and cost.

MIS and non-stoichiometric contact layers tune work function by transistor type to cut contact resistance, boost speed, and lower MOS voltages.

Segmented ferroelectric capacitor groups disconnect shared upper electrodes to preserve polarization during memory reads and avoid rewrite overhead.

Bridging wires link main and lead wires across flush board edges, enabling controller mounting without widening panel gaps or causing image anomalies.

Pixel-specific microlens shifts handle varying lens pupil distances while preserving PD uniformity, sensitivity, and color separation.

A first opening seats the light-emitting element and a second insulating layer fixes contacts, cutting mask steps, cost, and fabrication time.

A narrow-bandgap epitaxial layer shifts infrared detection beyond 850 nm to cut ambient background noise and improve photocurrent collection.

A thermocompression-bonded sheet conforms to stepped wafer surfaces, minimizing gaps, preventing chipping, and preserving useful chip area.

Parallel pad alignment on stacked optical chips widens pad spacing to suppress parasitic capacitance and protect high-speed signal quality.

Fixed-voltage edge pixels and PN junction-free or MIS boundary structures suppress dark current and blooming while reducing ineffective pixels.

An intermediate capping layer reduces silicon-germanium band discontinuities, cutting dark current in CMOS image sensors for accurate time-of-flight signals.

A backside deep trench isolation with conductive cap removes P-N junction leakage while preserving photodetector area and quantum efficiency.

A bent multi-directional drive transistor expands channel area in small pixels to cut charge-trapping noise and improve image quality.

Bonded epitaxial layer slices on a driver circuit substrate simplify micro-LED chip manufacturing, cutting process complexity and cost.

Dual-side laser dicing aligns front and back cuts on complex 3D memory wafers to reduce cracking, chipping, and yield loss.

Sequential Mn4+ doping in hydrofluoric acid forms core-shell fluoride phosphors that boost red emission efficiency for warm white LEDs.

Distributed resistive dividers let line sensors measure medium-voltage safely, reduce arcing risk, and harvest power for continuous monitoring.

Sequential imprint regions and protective layers enable large-area nano patterns on display substrates without losing nano-scale precision.

A light-impermeable layer with aligned openings places fingerprint sensing inside the display, preserving screen area without peripheral cutouts.

Floating mounting electrodes and laser repair enable defective micro-LED replacement while preserving high display resolution and panel reliability.

A containing-groove package aligns base-layer surfaces to cut height mismatch, avoid wire bonding, and simplify micro LED exposure.

Separated gas-jet regions keep substrates flat and at stable floating height, reducing deformation and uneven laser irradiation.

Side-edge gold fingers with a flexible buffer layer enable ultra-narrow bezels while protecting pads and keeping COF connections stable.

A density-tuned inorganic oxide layer improves charge transfer in stacked imaging elements while simplifying structure and easing manufacturing.

Selective insulation exposure and a current blocking layer help LEDs separate cleanly from the manufacturing substrate while preventing short circuits.

Opposing-stress film layers compensate substrate warpage, reducing lithography overlay errors in semiconductor fabrication.

A reflective shared-pixel layout combines visible and infrared detection to raise light sensitivity and quantum efficiency without separate pixels.

Buried insulator regions and a strained superlattice boost carrier mobility while combining localized SOI and bulk devices on one wafer.

Cross-linked polymer protective layers fill sub-10 nm gaps and resist wet etching, helping protect work function metal layers.

Recesses in an insulating layer guide fluid-transferred semiconductor units into aligned positions, improving connection quality and distribution uniformity.

A capping structure extends over active-layer edges to block etchant penetration, prevent voids, and protect image sensor reliability.

Substrate recesses or protrusions align terminals of different-thickness chips on one plane, enabling direct wiring and a thinner display.

A shared AC signal drives wired clocking and wireless transmission in a light detector, cutting circuit area and limiting interference.

Vertical connection wiring near the substrate cuts parasitic capacitance and supports clearer low-light imaging with lower noise.

Rare-earth and chromophore layers replace quantum dots in conversion pads, improving heat and light stability without toxic materials.

A deep trench isolation resonance layout uses reflective spacing and surface protrusions to return light to the intended pixel and improve QE.

A metal edge grid and inner air grid reduce spectral and spatial crosstalk between blue, green, and red pixel arrays to improve SNR.

A doped epitaxial bi-layer in backside deep trench isolation enlarges effective pixel area and improves quantum efficiency and full well capacity.

A front-side spectral router diverts parasitic light away from charge storage nodes while preserving back-side light collection in global shutter pixels.

Transferred single-crystal silicon plugs and source layers raise 3D memory mobility while reducing bonding defects and process complexity.

A tailored electron-acceptor layer extends organic photodetector absorption beyond 750 nm and improves photocurrent for near-infrared sensing.

Current limiting regions in micro-LED diode arrays cut sidewall non-radiative recombination and support more accurate mass transfer and inspection.

Conformal dielectric liners increase gate-to-contact spacing in 3D high-voltage fin transistors, improving breakdown margin and reliability.

A microlens-and-mask one-way filter passes collimated LED light while blocking ambient sunlight to keep exterior displays readable.

A sidewall PN junction in pixel isolation boosts saturated charge while maintaining pinning to suppress dark current in imaging elements.

Higher full-well panchromatic pixels and independent exposure control prevent early saturation and improve low-light image quality.

Integrated reflecting surfaces and overlapping photodetection regions shrink the package while preserving light emission and reception.

A wide-narrow deep trench layout cuts voids and substrate cracking while improving NIR sensitivity and cross-talk isolation in CMOS image sensors.

A wavelength-selective grating replaces fine RGB color films to preserve Micro-LED resolution while improving color purity and reducing color stringing.

A common electrode placed between the data line and pixel electrode cuts parasitic capacitance and crosstalk, improving display refresh rate and resolution.

Multiple optoelectronic components are lifted and placed sequentially on periodic contacts to cut transfer travel time without losing accuracy.

Selective film removal at the folding portion improves micro LED transfer accuracy while preventing protective film damage and rejects.