Monolithic Semiconductor Assembly Without Buried Oxide Isolation
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Solution Overview
Problem
Current semiconductor device assemblies using silicon-on-insulator (SOI) technologies are expensive due to high material and processing costs, and they suffer from poor thermal conductivity, which is inadequate for efficient heat dissipation in power semiconductor devices.
Innovation Solution
The semiconductor device assembly excludes a buried oxide layer and uses isolation trenches with dielectric material to electrically isolate monolithically integrated semiconductor devices, reducing costs and improving thermal dissipation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-on-insulator (SOI) technologies are used to isolate monolithically integrated devices, then electrical isolation between devices is improved, but material costs and processing costs increase significantly
Solution Approach 1:
The patent replaces expensive SOI wafers with standard silicon wafers, using a cost-effective alternative that achieves the same electrical isolation function through isolation trenches filled with dielectric material rather than requiring expensive pre-fabricated SOI structures
Solution Approach 2:
The patent extracts the isolation function from the substrate itself (SOI wafer) and implements it through separate isolation trenches that are etched and filled with dielectric material, allowing the use of standard silicon wafers instead of expensive SOI wafers
2Reliability
If silicon-on-insulator (SOI) technologies are used to isolate monolithically integrated devices, then electrical isolation is achieved, but thermal conductivity deteriorates due to buried oxide layers
Solution Approach 1:
The patent removes the buried oxide layer from the substrate structure, extracting the thermal resistance element and replacing it with isolation trenches that provide electrical isolation without compromising thermal conduction paths through the silicon substrate
Solution Approach 2:
The patent applies dielectric material locally in isolation trenches only where electrical isolation is needed between specific devices, while maintaining the bulk silicon substrate's superior thermal conductivity for heat dissipation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces material and manufacturing costs while enhancing thermal dissipation efficiency, making it a cost-effective and thermally efficient alternative to SOI technologies.
Implementation Method 1
an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate
Implementation Method 2
The semiconductor substrate can exclude a buried oxide layer... buried oxide layers included in SOI wafers have poor thermal conductivity, which is undesirable for providing efficient heat dissipation in power semiconductor devices
Data Source
AI summary
In a general aspect, a method includes forming, in a semiconductor device layer disposed on a semiconductor substrate, an opening between a first semiconductor device stack included in the semiconductor device layer and a second semiconductor device stack included in the semiconductor device layer. The method also includes forming a trench in the semiconductor substrate between the first semiconductor device stack and the second semiconductor device stack, the trench corresponding with the opening. The method further includes filling the trench with a first dielectric material, thinning the semiconductor substrate to expose the first dielectric material and separate the semiconductor substrate into a first substrate portion and a second substrate portion, and forming a layer of a second dielectric material on the first substrate portion, the second substrate portion and the exposed first dielectric material.