JBS Semiconductor Contact Layout for Surge Current Balancing

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Solution Overview

Problem

Conventional semiconductor devices face challenges in managing surge current, leading to delayed bipolar operation and potential destruction due to high contact resistance in p+-type regions, especially when the doping concentration of the n-type drift region varies, causing surge current to concentrate either in the chip center or outer periphery, resulting in localized heat generation and reduced surge current tolerance.

Innovation Solution

A semiconductor device with a JBS structure is designed, featuring a varying distribution of nickel silicide films and ohmic regions based on the doping concentration of the n-type drift region, where the number and area of ohmic regions are adjusted in the chip center and outer peripheral portions to disperse surge current and prevent destruction, with specific contact resistances and area ratios optimized for low Vf characteristics and enhanced surge current tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the doping concentration of the n-type drift region is increased, then the forward voltage is reduced, but the surge current concentrates in the chip center causing localized heat generation and reduced surge current tolerance

Engineering Contradiction:
Improveforward voltageVSAvoidsurge current tolerance
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating different doping concentration zones within the n-type drift region. The chip center portion has a first doping concentration while the outer peripheral portion has a second doping concentration, allowing each region to be optimized for its specific function - the center for low forward voltage and the periphery for surge current dissipation

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the n-type drift region into multiple concentration zones based on their functional requirements. By dividing the uniform doping structure into differentiated zones (chip center vs. outer periphery), the patent enables independent optimization of forward voltage characteristics and surge current tolerance in each segment

Inventive Principle:
Principle #1Segmentation

2Reliability

If the doping concentration of the n-type drift region is decreased, then the surge current tolerance is improved, but the forward voltage increases

Engineering Contradiction:
Improvesurge current toleranceVSAvoidforward voltage
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by creating different doping concentration zones within the n-type drift region. The chip center portion has a first doping concentration while the outer peripheral portion has a second doping concentration, allowing each region to be optimized for its specific function - the center for low forward voltage and the periphery for surge current dissipation

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the n-type drift region into multiple concentration zones based on their functional requirements. By dividing the uniform doping structure into differentiated zones (chip center vs. outer periphery), the patent enables independent optimization of forward voltage characteristics and surge current tolerance in each segment

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If uniform silicide films are provided across the entire active region, then the manufacturing process is simplified, but the surge current distribution becomes unbalanced causing localized heat generation

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidlocalized heat generation
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent applies local quality by providing different densities of silicide films in different regions of the active region. The chip center portion has a first silicide film density while the outer peripheral portion has a second silicide film density, creating localized variations in contact resistance that balance the surge current distribution and prevent hot spots

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the silicide film distribution into different density zones corresponding to the functional zones of the device. This segmentation allows the contact resistance to be optimized in each region - lower in the center for efficient current collection and higher in the periphery for surge current dissipation

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively disperses surge current and maintains low forward voltage characteristics, enhancing surge current tolerance and preventing localized heat generation by adjusting the distribution of ohmic regions and contact resistances according to the doping concentration of the n-type drift region, thereby improving the reliability of the semiconductor device.

Implementation Method 1

a plurality of silicide films each in ohmic contact with a portion of a corresponding one of the plurality of second-conductivity-type regions

Methodology Applied
Scientific EffectOhmic contact: Conduction (electrical)

Data Source

PatentUS20250107119A1Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2025.03.27 FUJI ELECTRIC CO LTD
  • US20250107119A1 patent drawing
  • US20250107119A1 patent drawing
  • US20250107119A1 patent drawing

AI summary

A semiconductor device includes an active region, a first-conductivity-type region, and a termination region. The active region has first second-conductivity-type regions, silicide films, and a first electrode; the termination region has a second second-conductivity-type region. The active region is configured by ohmic regions where the first electrode is in contact with the silicide films, and Schottky regions where the first electrode is in contact with the first-conductivity-type region. When a doping concentration of the first-conductivity-type region is a low concentration, a greater number of the ohmic regions is provided in a chip center portion than in a chip outer peripheral portion and when the doping concentration of the first-conductivity-type region is a high concentration, a greater number of the ohmic regions is provided in the chip outer peripheral portion than in the chip center portion.