3D Memory Stack Bonding With Single-Crystal Silicon Plugs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D NAND memory devices face limitations in performance and density due to the use of polycrystalline silicon inter-deck plugs and source layers, which result in carrier mobility loss and increased fabrication complexity, and the hybrid bonding process requires high alignment accuracy and can introduce voids, impacting device yield.
Innovation Solution
The use of single-crystal silicon layers transferred via a de-bonding process for forming multi-deck and multi-stack 3D memory devices, replacing polycrystalline silicon with single-crystal silicon for inter-deck plugs and source layers, and bonding using a silicon-dielectric process, along with forming interconnects on dedicated donor substrates and transferring them to the memory device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polycrystalline silicon is used for inter-deck plugs and source layers, then fabrication process is simpler, but carrier mobility is reduced and performance deteriorates
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to single-crystal silicon, fundamentally altering the crystal structure to eliminate grain boundaries. This parameter change directly improves carrier mobility while the transfer bonding process manages the fabrication complexity
Solution Approach 2:
The patent introduces a transfer substrate as an intermediary carrier that temporarily holds the single-crystal silicon layer before transferring it to the final device structure. This mediator enables the use of high-quality single-crystal material without requiring direct growth in the final configuration, thus managing fabrication complexity
2Manufacturing precision
If hybrid bonding process is used for stacking, then alignment accuracy can be achieved, but voids are introduced and device yield decreases
Solution Approach 1:
The patent extracts the bonding function from the traditional hybrid bonding process and replaces it with a transfer bonding mechanism. The single-crystal silicon layer is transferred from a separate substrate, eliminating the harmful void formation associated with hybrid bonding while maintaining alignment accuracy through the transfer substrate approach
Solution Approach 2:
The patent creates a copy of the single-crystal silicon layer on a transfer substrate, which can then be precisely positioned and transferred to the target location. This copying approach enables high alignment accuracy without the defects of direct hybrid bonding, as the transfer process allows for better control and void prevention
3Productivity
If traditional fabrication process is used, then manufacturing steps are numerous, but cycle time is extended and productivity is reduced
Solution Approach 1:
The patent merges multiple fabrication operations into the transfer bonding process. By forming the single-crystal silicon layer and interconnect structures on a separate transfer substrate and then transferring them as an integrated unit, the process combines what would otherwise be separate deposition, patterning, and bonding steps into a more efficient sequence
Solution Approach 2:
The patent performs preliminary formation of the single-crystal silicon layer and associated structures on a transfer substrate before final assembly. This preliminary action on a dedicated substrate allows for optimized process conditions and enables parallel processing, reducing the overall fabrication cycle time when the transferred structure is integrated into the final device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility, increases cell storage capacity, improves electrical performance, and reduces fabrication complexity and cycle time, while providing higher yield and bonding strength compared to traditional methods.
Implementation Method 1
The use of single-crystal silicon layers transferred via a de-bonding process for forming multi-deck and multi-stack 3D memory devices
Implementation Method 2
bonding using a silicon-dielectric process, along with forming interconnects on dedicated donor substrates and transferring them to the memory device structure
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Disclosed are three-dimensional (3D) memory devices and methods for forming the 3D memory devices. In an example, a 3D memory device (100) includes a substrate (102), a first single-crystal silicon layer (118) above the substrate (102), a first memory stack (120) above the first single-crystal silicon layer (118), a first channel structure (122) extending vertically through the first memory stack (120), and a first interconnect layer (140) above the first memory stack (120). The first memory stack (120) includes a first plurality of interleaved conductor layers and dielectric layers. The first channel structure (122) includes a first lower plug (130) extending into the first single-crystal silicon layer (118) and including single-crystal silicon. The first interconnect layer (140) includes a first bit line (142) electrically connected to the first channel structure (122).