Localized SOI Superlattice Wafer Structure for Carrier Mobility
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Solution Overview
Problem
Current semiconductor devices do not fully leverage advanced materials and processing techniques to achieve optimal performance enhancements, particularly in charge carrier mobility and integration of semiconductor-on-insulator (SOI) regions.
Innovation Solution
The method involves forming buried insulator regions in a semiconductor substrate, creating localized SOI and bulk semiconductor regions, and constructing a superlattice with stacked semiconductor and non-semiconductor monolayers to enhance charge carrier mobility and integrate optical waveguides, memory circuits, and other devices on the same wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained material layers are used to enhance charge carrier mobility, then device speed and performance are improved, but manufacturing complexity increases due to multiple layer deposition and strain control requirements
Solution Approach 1:
The patent applies local quality by creating localized SOI regions with strained material layers only in specific areas where high-speed devices are needed, while other regions maintain bulk semiconductor characteristics. This allows mobility enhancement to be applied selectively to individual devices or device regions rather than uniformly across the entire wafer, thereby improving charge carrier mobility where required while limiting the increase in manufacturing complexity to only the affected local regions.
Solution Approach 2:
The patent employs composite materials by integrating multiple material systems including silicon, silicon-germanium, and insulator layers in a layered superlattice structure. The strained silicon layers are combined with relaxation layers and buried insulator regions to create a composite structure that provides both the strain necessary for high mobility and the structural stability required for manufacturing. This composite approach enables mobility enhancement while managing the complexity through established material compatibility.
2Reliability
If buried insulator regions are formed to create localized SOI structures, then device performance is enhanced through mobility improvement, but manufacturing steps and process complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor wafer into distinct regions: localized SOI regions with buried insulators and strained layers for high-performance devices, and bulk semiconductor regions for standard devices. The buried insulator regions are formed as discrete segments rather than a continuous layer, allowing selective application of complex processing steps only where needed. This segmentation enables performance enhancement in specific devices without requiring complex processing across the entire wafer.
Solution Approach 2:
The patent employs preliminary action by forming the buried insulator regions and strained material layers during the early stages of device fabrication, before final device formation. The localized SOI structures are prepared in advance with pre-formed insulator regions and strained layers, allowing subsequent device processing to proceed with simplified steps. This preliminary structuring enables performance enhancement to be built into the substrate before device-specific processing begins.
3Reliability
If superlattice structures with multiple monolayers are constructed to enhance mobility, then charge carrier conductivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the thickness, composition, and strain state of individual layers within the superlattice structure. By carefully controlling parameters such as silicon-germanium composition ratios, layer thicknesses in the range of nanometers, and strain magnitudes, the patent optimizes charge carrier mobility while maintaining manufacturability. These parameter optimizations allow the superlattice to provide enhanced conductivity through controlled strain effects rather than requiring extremely precise atomic-level layer control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves charge carrier mobility, reduces scattering effects, and enables the integration of both bulk and SOI devices on a single wafer, offering enhanced performance and cost-effectiveness by utilizing MST technology for improved conductivity and dopant retention.
Implementation Method 1
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 2
forming buried spaced-apart insulator regions in a semiconductor substrate, and forming a monocrystalline semiconductor layer on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions
Data Source
AI summary
A method for making a semiconductor device may include forming buried spaced-apart insulator regions in a semiconductor substrate, and forming a monocrystalline semiconductor layer on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions. The method may also include forming a superlattice in the monocrystalline semiconductor layer. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming semiconductor devices in the monocrystalline layer, with some of the semiconductor devices in the localized SOI regions, and some other semiconductor devices in the localized bulk semiconductor regions.