Dual-Side Wafer Dicing Alignment for 3D Memory Yield
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Solution Overview
Problem
The increasing demands for higher integration in semiconductor devices, particularly 3D memory devices, face challenges in wafer dicing due to complex metal layer structures containing tungsten, which hinder efficient cleaving and lead to cracks, chipping, and low yield, as existing dicing methods struggle with aligning dicing positions on both sides of the wafer.
Innovation Solution
A wafer dicing device comprising a bearing platform and two dicing sub-devices that allow simultaneous dicing from both the front and back sides, with alignable focusing lenses and lasers, enabling precise alignment and efficient dicing through the use of movable or fixed lens positions and optical path conversion using mirrors to reduce errors and increase dicing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing single-side dicing methods are used, then device complexity is reduced, but dicing precision and yield deteriorate due to alignment difficulties and mechanical stress on complex 3D memory structures
Solution Approach 1:
The dicing process is segmented into two independent operations: front-side dicing and back-side dicing. Each side is processed separately by dedicated dicing devices, allowing precise control and alignment for each operation without the complexity of simultaneous multi-axis coordination.
Solution Approach 2:
The invention transitions from single-side dicing to dual-side dicing by adding the dimensional aspect of processing from both front and back surfaces. This enables precise positioning and reduced mechanical stress by approaching the dicing plane from opposite directions.
2Productivity
If simultaneous dual-side dicing is implemented, then dicing efficiency improves, but device complexity and alignment difficulty increase
Solution Approach 1:
The simultaneous dual-side dicing system is segmented into independent front-side and back-side dicing subsystems. Each subsystem operates autonomously with its own dicing device, allowing high productivity through parallel processing while maintaining manageable complexity by avoiding integrated multi-axis control.
Solution Approach 2:
Two separate dicing operations are merged into a simultaneous process by coordinating front-side and back-side dicing devices to operate concurrently on the same wafer, doubling productivity while keeping each subsystem relatively simple and independent.
3Reliability
If simultaneous dual-side dicing is implemented, then yield improves, but alignment precision difficulty increases
Solution Approach 1:
Alignment is segmented into two independent alignment operations: front-side alignment and back-side alignment. Each alignment operation is performed separately by its respective dicing device, allowing optimized alignment procedures for each side without the compounded complexity of simultaneous multi-point alignment.
Solution Approach 2:
The alignment process utilizes both front and back surfaces as separate dimensional references. By establishing alignment markers and reference points on both sides, the system achieves high yield through dual-dimensional verification and correction, reducing the impact of single-side alignment errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances dicing efficiency and yield by allowing simultaneous front and back side dicing, reducing alignment difficulties and mechanical stress, thereby improving the processing of complex 3D memory devices with multiple tiers and metal layers.
Implementation Method 1
a first dicing sub device (111) configured to dice the wafer to be diced (102) from a first side; and a second dicing sub device (112) configured to dice the wafer to be diced (102) from a second side
Implementation Method 2
alignable focusing lenses and lasers, enabling precise alignment
Data Source
AI summary
Examples of the present disclosure provide a wafer dicing device and a method of wafer dicing, the wafer dicing device including: a bearing platform, a first dicing sub device and a second dicing sub device, wherein the bearing platform is configured to bear the wafer to be diced, the first dicing sub device is configured to dice the wafer to be diced from a first side, and the second dicing sub device is configured to dice the wafer to be diced from a second side, the first side and the second side being opposite sides of the bearing platform in a first direction, the first direction being a direction of the thickness of the bearing platform.