Vertical Channel Memory Structure With Separated Drain Select Plugs
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Solution Overview
Problem
Existing semiconductor memory devices with nonvolatile memory technology face challenges in achieving high write and read speeds while maintaining data integrity even when power is cut off.
Innovation Solution
A semiconductor memory device with a vertical channel structure is designed, featuring a lower stack with alternating interlayer insulating and conductive layers, cell plugs, an upper stack with additional interlayer insulating and conductive layers, and drain select plugs separated by a separation pattern. This configuration allows for efficient separation of select lines in the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a vertical channel structure is used to improve write and read speeds, then access speed is improved, but device complexity increases due to the need for separation patterns and multi-stack configuration
Solution Approach 1:
The memory device is divided into a lower stack and an upper stack, with cell plugs passing through the lower stack and drain select plugs passing through the upper stack. This segmentation allows for separate control of cell selection and drain selection functions, improving access speed while managing complexity through functional division.
Solution Approach 2:
The patent transitions from a planar memory structure to a vertical channel structure with plugs extending in the vertical direction. This dimensional change enables higher density and faster access by utilizing the vertical dimension for signal transmission and cell organization.
2Measurement precision
If select lines are separated using a separation pattern, then control precision is improved, but manufacturing precision requirements increase
Solution Approach 1:
A separation pattern is introduced as an intermediary structure between adjacent drain select plugs. This separation pattern provides electrical isolation and precise control of select lines, improving control precision while the alternating interlayer insulating layers provide a structured framework that facilitates manufacturing.
Solution Approach 2:
The device uses alternating interlayer insulating layers and conductive layers forming a composite stack structure. This composite approach allows for integrated control of electrical isolation and conductive pathways, achieving precise control while managing manufacturing complexity through a unified layered architecture.
Data Source
AI summary
A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.