Stacked Optical Chip Pad Layout for Parasitic Capacitance Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In optical communication devices, the miniaturization trend leads to increased parasitic capacitance due to closer channel arrangements, affecting high-frequency signal quality, especially at higher transmission rates like 64 Gbaud, where electrostatic capacitance between pads and the substrate degrades signal quality.
Innovation Solution
The optical communication device design features electrode pads on semiconductor chips positioned such that their center points lie on parallel straight lines, reducing parasitic capacitance by widening the intervals between pads and maintaining signal quality, even at higher transmission rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If channels are arranged closer together to achieve miniaturization, then device size is reduced, but parasitic capacitance increases and high-frequency signal quality deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of pads to a three-dimensional stacked arrangement. First chip and second chip are positioned at different heights (vertical dimension), with pads on each chip arranged on parallel straight lines. This spatial separation in the vertical dimension reduces parasitic capacitance between corresponding pads while maintaining compact horizontal footprint, thus achieving miniaturization without sacrificing signal quality.
2Reliability
If pad size is increased to ensure reliable electrical connection, then connection reliability is improved, but parasitic capacitance increases and high-frequency characteristics deteriorate
Solution Approach 1:
The patent changes the spatial parameter of pad arrangement by positioning pad centers on parallel straight lines rather than in a grid pattern. This specific geometric configuration, combined with the vertical stacking of chips, optimizes the electric field distribution and reduces parasitic capacitance while maintaining adequate pad size for reliable electrical connection.
3Productivity
If transmission rate is increased to achieve higher communication capacity, then communication capacity is improved, but signal quality deteriorates due to increased sensitivity to parasitic capacitance
Solution Approach 1:
By utilizing the vertical dimension through chip stacking, the patent reduces the horizontal area required for pad arrangements. This allows corresponding pads to be positioned closer in the vertical direction while maintaining appropriate horizontal spacing, thereby reducing parasitic capacitance effects that would otherwise limit high-speed signal transmission and enabling higher communication capacities.
Data Source
AI summary
An optical communication device includes: a semiconductor chip that includes an optical waveguide formed in the semiconductor chip, and G pads, a P pad, and S pads for outputting electrical signals indicating intensity of light propagating in the optical waveguide; and a semiconductor chip that includes G pads and S pads electrically connected to the G pads, the P pad, and the S pads, and is connected to the semiconductor chip, wherein the center points of at least some of the S pads are located on straight lines on at least one of the chips, the straight lines being parallel to sides, and the center points of the other electrode pads are located on other straight lines farther from the sides than the straight lines.